evm.c 6.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2004-2011
  4. * Texas Instruments, <www.ti.com>
  5. *
  6. * Author :
  7. * Manikandan Pillai <mani.pillai@ti.com>
  8. *
  9. * Derived from Beagle Board and 3430 SDP code by
  10. * Richard Woodruff <r-woodruff2@ti.com>
  11. * Syed Mohammed Khasim <khasim@ti.com>
  12. */
  13. #include <common.h>
  14. #include <dm.h>
  15. #include <env.h>
  16. #include <init.h>
  17. #include <net.h>
  18. #include <ns16550.h>
  19. #include <serial.h>
  20. #include <asm/global_data.h>
  21. #include <asm/io.h>
  22. #include <asm/arch/mem.h>
  23. #include <asm/arch/mux.h>
  24. #include <asm/arch/sys_proto.h>
  25. #include <asm/arch/mmc_host_def.h>
  26. #include <asm/gpio.h>
  27. #include <twl4030.h>
  28. #include <asm/mach-types.h>
  29. #include <linux/delay.h>
  30. #include <linux/mtd/rawnand.h>
  31. #include "evm.h"
  32. #define OMAP3EVM_GPIO_ETH_RST_GEN1 64
  33. #define OMAP3EVM_GPIO_ETH_RST_GEN2 7
  34. #define CONFIG_SMC911X_BASE 0x2C000000
  35. DECLARE_GLOBAL_DATA_PTR;
  36. static u32 omap3_evm_version;
  37. u32 get_omap3_evm_rev(void)
  38. {
  39. return omap3_evm_version;
  40. }
  41. static void omap3_evm_get_revision(void)
  42. {
  43. #if defined(CONFIG_SMC911X)
  44. /*
  45. * Board revision can be ascertained only by identifying
  46. * the Ethernet chipset.
  47. */
  48. unsigned int smsc_id;
  49. /* Ethernet PHY ID is stored at ID_REV register */
  50. smsc_id = readl(CONFIG_SMC911X_BASE + 0x50) & 0xFFFF0000;
  51. printf("Read back SMSC id 0x%x\n", smsc_id);
  52. switch (smsc_id) {
  53. /* SMSC9115 chipset */
  54. case 0x01150000:
  55. omap3_evm_version = OMAP3EVM_BOARD_GEN_1;
  56. break;
  57. /* SMSC 9220 chipset */
  58. case 0x92200000:
  59. default:
  60. omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
  61. }
  62. #else /* !CONFIG_SMC911X */
  63. #if defined(CONFIG_STATIC_BOARD_REV)
  64. /* Look for static defintion of the board revision */
  65. omap3_evm_version = CONFIG_STATIC_BOARD_REV;
  66. #else
  67. /* Fallback to the default above */
  68. omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
  69. #endif /* CONFIG_STATIC_BOARD_REV */
  70. #endif /* CONFIG_SMC911X */
  71. }
  72. #if defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)
  73. /* MUSB port on OMAP3EVM Rev >= E requires extvbus programming. */
  74. u8 omap3_evm_need_extvbus(void)
  75. {
  76. u8 retval = 0;
  77. if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
  78. retval = 1;
  79. return retval;
  80. }
  81. #endif /* CONFIG_USB_MUSB_{GADGET,HOST} */
  82. /*
  83. * Routine: board_init
  84. * Description: Early hardware init.
  85. */
  86. int board_init(void)
  87. {
  88. gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
  89. /* board id for Linux */
  90. gd->bd->bi_arch_number = MACH_TYPE_OMAP3EVM;
  91. /* boot param addr */
  92. gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
  93. return 0;
  94. }
  95. #if defined(CONFIG_SPL_OS_BOOT)
  96. int spl_start_uboot(void)
  97. {
  98. /* break into full u-boot on 'c' */
  99. if (serial_tstc() && serial_getc() == 'c')
  100. return 1;
  101. return 0;
  102. }
  103. #endif /* CONFIG_SPL_OS_BOOT */
  104. #if defined(CONFIG_SPL_BUILD)
  105. /*
  106. * Routine: get_board_mem_timings
  107. * Description: If we use SPL then there is no x-loader nor config header
  108. * so we have to setup the DDR timings ourself on the first bank. This
  109. * provides the timing values back to the function that configures
  110. * the memory.
  111. */
  112. void get_board_mem_timings(struct board_sdrc_timings *timings)
  113. {
  114. int pop_mfr, pop_id;
  115. /*
  116. * We need to identify what PoP memory is on the board so that
  117. * we know what timings to use. To map the ID values please see
  118. * nand_ids.c
  119. */
  120. identify_nand_chip(&pop_mfr, &pop_id);
  121. if (pop_mfr == NAND_MFR_HYNIX && pop_id == 0xbc) {
  122. /* 256MB DDR */
  123. timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
  124. timings->ctrla = HYNIX_V_ACTIMA_200;
  125. timings->ctrlb = HYNIX_V_ACTIMB_200;
  126. } else {
  127. /* 128MB DDR */
  128. timings->mcfg = MICRON_V_MCFG_165(128 << 20);
  129. timings->ctrla = MICRON_V_ACTIMA_165;
  130. timings->ctrlb = MICRON_V_ACTIMB_165;
  131. }
  132. timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
  133. timings->mr = MICRON_V_MR_165;
  134. }
  135. #endif /* CONFIG_SPL_BUILD */
  136. /*
  137. * Routine: misc_init_r
  138. * Description: Init ethernet (done here so udelay works)
  139. */
  140. int misc_init_r(void)
  141. {
  142. twl4030_power_init();
  143. #if defined(CONFIG_SMC911X)
  144. setup_net_chip();
  145. #endif
  146. omap3_evm_get_revision();
  147. #if defined(CONFIG_SMC911X)
  148. reset_net_chip();
  149. #endif
  150. omap_die_id_display();
  151. #if defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET) && \
  152. !defined(CONFIG_SMC911X)
  153. omap_die_id_usbethaddr();
  154. #endif
  155. return 0;
  156. }
  157. /*
  158. * Routine: set_muxconf_regs
  159. * Description: Setting up the configuration Mux registers specific to the
  160. * hardware. Many pins need to be moved from protect to primary
  161. * mode.
  162. */
  163. void set_muxconf_regs(void)
  164. {
  165. MUX_EVM();
  166. }
  167. #if defined(CONFIG_SMC911X)
  168. /*
  169. * Routine: setup_net_chip
  170. * Description: Setting up the configuration GPMC registers specific to the
  171. * Ethernet hardware.
  172. */
  173. static void setup_net_chip(void)
  174. {
  175. struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
  176. /* Configure GPMC registers */
  177. writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1);
  178. writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2);
  179. writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3);
  180. writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4);
  181. writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5);
  182. writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6);
  183. writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7);
  184. /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
  185. writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
  186. /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
  187. writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
  188. /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
  189. writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
  190. &ctrl_base->gpmc_nadv_ale);
  191. }
  192. /**
  193. * Reset the ethernet chip.
  194. */
  195. static void reset_net_chip(void)
  196. {
  197. int ret;
  198. int rst_gpio;
  199. if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1) {
  200. rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN1;
  201. } else {
  202. rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN2;
  203. }
  204. ret = gpio_request(rst_gpio, "");
  205. if (ret < 0) {
  206. printf("Unable to get GPIO %d\n", rst_gpio);
  207. return ;
  208. }
  209. /* Configure as output */
  210. gpio_direction_output(rst_gpio, 0);
  211. /* Send a pulse on the GPIO pin */
  212. gpio_set_value(rst_gpio, 1);
  213. udelay(1);
  214. gpio_set_value(rst_gpio, 0);
  215. udelay(1);
  216. gpio_set_value(rst_gpio, 1);
  217. }
  218. #endif /* CONFIG_SMC911X */
  219. #if defined(CONFIG_MMC)
  220. void board_mmc_power_init(void)
  221. {
  222. twl4030_power_mmc_init(0);
  223. }
  224. #endif /* CONFIG_MMC */