evm.c 31 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013
  4. * Texas Instruments Incorporated, <www.ti.com>
  5. *
  6. * Lokesh Vutla <lokeshvutla@ti.com>
  7. *
  8. * Based on previous work by:
  9. * Aneesh V <aneesh@ti.com>
  10. * Steve Sakoman <steve@sakoman.com>
  11. */
  12. #include <common.h>
  13. #include <env.h>
  14. #include <fdt_support.h>
  15. #include <fastboot.h>
  16. #include <image.h>
  17. #include <init.h>
  18. #include <spl.h>
  19. #include <net.h>
  20. #include <palmas.h>
  21. #include <sata.h>
  22. #include <serial.h>
  23. #include <asm/global_data.h>
  24. #include <linux/string.h>
  25. #include <asm/gpio.h>
  26. #include <usb.h>
  27. #include <linux/usb/gadget.h>
  28. #include <asm/omap_common.h>
  29. #include <asm/omap_sec_common.h>
  30. #include <asm/arch/gpio.h>
  31. #include <asm/arch/dra7xx_iodelay.h>
  32. #include <asm/emif.h>
  33. #include <asm/arch/sys_proto.h>
  34. #include <asm/arch/mmc_host_def.h>
  35. #include <asm/arch/sata.h>
  36. #include <dwc3-uboot.h>
  37. #include <dwc3-omap-uboot.h>
  38. #include <i2c.h>
  39. #include <ti-usb-phy-uboot.h>
  40. #include "mux_data.h"
  41. #include "../common/board_detect.h"
  42. #define board_is_dra76x_evm() board_ti_is("DRA76/7x")
  43. #define board_is_dra74x_evm() board_ti_is("5777xCPU")
  44. #define board_is_dra72x_evm() board_ti_is("DRA72x-T")
  45. #define board_is_dra71x_evm() board_ti_is("DRA79x,D")
  46. #define board_is_dra74x_revh_or_later() (board_is_dra74x_evm() && \
  47. (strncmp("H", board_ti_get_rev(), 1) <= 0))
  48. #define board_is_dra72x_revc_or_later() (board_is_dra72x_evm() && \
  49. (strncmp("C", board_ti_get_rev(), 1) <= 0))
  50. #define board_ti_get_emif_size() board_ti_get_emif1_size() + \
  51. board_ti_get_emif2_size()
  52. DECLARE_GLOBAL_DATA_PTR;
  53. /* GPIO 7_11 */
  54. #define GPIO_DDR_VTT_EN 203
  55. #define SYSINFO_BOARD_NAME_MAX_LEN 37
  56. /* I2C I/O Expander */
  57. #define NAND_PCF8575_ADDR 0x21
  58. #define NAND_PCF8575_I2C_BUS_NUM 0
  59. const struct omap_sysinfo sysinfo = {
  60. "Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n"
  61. };
  62. static const struct emif_regs emif1_ddr3_532_mhz_1cs = {
  63. .sdram_config_init = 0x61851ab2,
  64. .sdram_config = 0x61851ab2,
  65. .sdram_config2 = 0x08000000,
  66. .ref_ctrl = 0x000040F1,
  67. .ref_ctrl_final = 0x00001035,
  68. .sdram_tim1 = 0xCCCF36B3,
  69. .sdram_tim2 = 0x308F7FDA,
  70. .sdram_tim3 = 0x427F88A8,
  71. .read_idle_ctrl = 0x00050000,
  72. .zq_config = 0x0007190B,
  73. .temp_alert_config = 0x00000000,
  74. .emif_ddr_phy_ctlr_1_init = 0x0024400B,
  75. .emif_ddr_phy_ctlr_1 = 0x0E24400B,
  76. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  77. .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  78. .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  79. .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
  80. .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
  81. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  82. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  83. .emif_rd_wr_lvl_ctl = 0x00000000,
  84. .emif_rd_wr_exec_thresh = 0x00000305
  85. };
  86. static const struct emif_regs emif2_ddr3_532_mhz_1cs = {
  87. .sdram_config_init = 0x61851B32,
  88. .sdram_config = 0x61851B32,
  89. .sdram_config2 = 0x08000000,
  90. .ref_ctrl = 0x000040F1,
  91. .ref_ctrl_final = 0x00001035,
  92. .sdram_tim1 = 0xCCCF36B3,
  93. .sdram_tim2 = 0x308F7FDA,
  94. .sdram_tim3 = 0x427F88A8,
  95. .read_idle_ctrl = 0x00050000,
  96. .zq_config = 0x0007190B,
  97. .temp_alert_config = 0x00000000,
  98. .emif_ddr_phy_ctlr_1_init = 0x0024400B,
  99. .emif_ddr_phy_ctlr_1 = 0x0E24400B,
  100. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  101. .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  102. .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  103. .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
  104. .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
  105. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  106. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  107. .emif_rd_wr_lvl_ctl = 0x00000000,
  108. .emif_rd_wr_exec_thresh = 0x00000305
  109. };
  110. static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
  111. .sdram_config_init = 0x61862B32,
  112. .sdram_config = 0x61862B32,
  113. .sdram_config2 = 0x08000000,
  114. .ref_ctrl = 0x0000514C,
  115. .ref_ctrl_final = 0x0000144A,
  116. .sdram_tim1 = 0xD113781C,
  117. .sdram_tim2 = 0x30717FE3,
  118. .sdram_tim3 = 0x409F86A8,
  119. .read_idle_ctrl = 0x00050000,
  120. .zq_config = 0x5007190B,
  121. .temp_alert_config = 0x00000000,
  122. .emif_ddr_phy_ctlr_1_init = 0x0024400D,
  123. .emif_ddr_phy_ctlr_1 = 0x0E24400D,
  124. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  125. .emif_ddr_ext_phy_ctrl_2 = 0x00A400A4,
  126. .emif_ddr_ext_phy_ctrl_3 = 0x00A900A9,
  127. .emif_ddr_ext_phy_ctrl_4 = 0x00B000B0,
  128. .emif_ddr_ext_phy_ctrl_5 = 0x00B000B0,
  129. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  130. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  131. .emif_rd_wr_lvl_ctl = 0x00000000,
  132. .emif_rd_wr_exec_thresh = 0x00000305
  133. };
  134. const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = {
  135. .sdram_config_init = 0x61862BB2,
  136. .sdram_config = 0x61862BB2,
  137. .sdram_config2 = 0x00000000,
  138. .ref_ctrl = 0x0000514D,
  139. .ref_ctrl_final = 0x0000144A,
  140. .sdram_tim1 = 0xD1137824,
  141. .sdram_tim2 = 0x30B37FE3,
  142. .sdram_tim3 = 0x409F8AD8,
  143. .read_idle_ctrl = 0x00050000,
  144. .zq_config = 0x5007190B,
  145. .temp_alert_config = 0x00000000,
  146. .emif_ddr_phy_ctlr_1_init = 0x0824400E,
  147. .emif_ddr_phy_ctlr_1 = 0x0E24400E,
  148. .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
  149. .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
  150. .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
  151. .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
  152. .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
  153. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  154. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  155. .emif_rd_wr_lvl_ctl = 0x00000000,
  156. .emif_rd_wr_exec_thresh = 0x00000305
  157. };
  158. const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = {
  159. .sdram_config_init = 0x61851ab2,
  160. .sdram_config = 0x61851ab2,
  161. .sdram_config2 = 0x08000000,
  162. .ref_ctrl = 0x000040F1,
  163. .ref_ctrl_final = 0x00001035,
  164. .sdram_tim1 = 0xCCCF36B3,
  165. .sdram_tim2 = 0x30BF7FDA,
  166. .sdram_tim3 = 0x427F8BA8,
  167. .read_idle_ctrl = 0x00050000,
  168. .zq_config = 0x0007190B,
  169. .temp_alert_config = 0x00000000,
  170. .emif_ddr_phy_ctlr_1_init = 0x0024400B,
  171. .emif_ddr_phy_ctlr_1 = 0x0E24400B,
  172. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  173. .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  174. .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  175. .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
  176. .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
  177. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  178. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  179. .emif_rd_wr_lvl_ctl = 0x00000000,
  180. .emif_rd_wr_exec_thresh = 0x00000305
  181. };
  182. const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = {
  183. .sdram_config_init = 0x61851B32,
  184. .sdram_config = 0x61851B32,
  185. .sdram_config2 = 0x08000000,
  186. .ref_ctrl = 0x000040F1,
  187. .ref_ctrl_final = 0x00001035,
  188. .sdram_tim1 = 0xCCCF36B3,
  189. .sdram_tim2 = 0x308F7FDA,
  190. .sdram_tim3 = 0x427F88A8,
  191. .read_idle_ctrl = 0x00050000,
  192. .zq_config = 0x0007190B,
  193. .temp_alert_config = 0x00000000,
  194. .emif_ddr_phy_ctlr_1_init = 0x0024400B,
  195. .emif_ddr_phy_ctlr_1 = 0x0E24400B,
  196. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  197. .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  198. .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  199. .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
  200. .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
  201. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  202. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  203. .emif_rd_wr_lvl_ctl = 0x00000000,
  204. .emif_rd_wr_exec_thresh = 0x00000305
  205. };
  206. const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra76 = {
  207. .sdram_config_init = 0x61862B32,
  208. .sdram_config = 0x61862B32,
  209. .sdram_config2 = 0x00000000,
  210. .ref_ctrl = 0x0000514C,
  211. .ref_ctrl_final = 0x0000144A,
  212. .sdram_tim1 = 0xD113783C,
  213. .sdram_tim2 = 0x30B47FE3,
  214. .sdram_tim3 = 0x409F8AD8,
  215. .read_idle_ctrl = 0x00050000,
  216. .zq_config = 0x5007190B,
  217. .temp_alert_config = 0x00000000,
  218. .emif_ddr_phy_ctlr_1_init = 0x0824400D,
  219. .emif_ddr_phy_ctlr_1 = 0x0E24400D,
  220. .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
  221. .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
  222. .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
  223. .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
  224. .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
  225. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  226. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  227. .emif_rd_wr_lvl_ctl = 0x00000000,
  228. .emif_rd_wr_exec_thresh = 0x00000305
  229. };
  230. const struct emif_regs emif_2_regs_ddr3_666_mhz_1cs_dra76 = {
  231. .sdram_config_init = 0x61862B32,
  232. .sdram_config = 0x61862B32,
  233. .sdram_config2 = 0x00000000,
  234. .ref_ctrl = 0x0000514C,
  235. .ref_ctrl_final = 0x0000144A,
  236. .sdram_tim1 = 0xD113781C,
  237. .sdram_tim2 = 0x30B47FE3,
  238. .sdram_tim3 = 0x409F8AD8,
  239. .read_idle_ctrl = 0x00050000,
  240. .zq_config = 0x5007190B,
  241. .temp_alert_config = 0x00000000,
  242. .emif_ddr_phy_ctlr_1_init = 0x0824400D,
  243. .emif_ddr_phy_ctlr_1 = 0x0E24400D,
  244. .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
  245. .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
  246. .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
  247. .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
  248. .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
  249. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  250. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  251. .emif_rd_wr_lvl_ctl = 0x00000000,
  252. .emif_rd_wr_exec_thresh = 0x00000305
  253. };
  254. void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
  255. {
  256. u64 ram_size;
  257. ram_size = board_ti_get_emif_size();
  258. switch (omap_revision()) {
  259. case DRA752_ES1_0:
  260. case DRA752_ES1_1:
  261. case DRA752_ES2_0:
  262. switch (emif_nr) {
  263. case 1:
  264. if (ram_size > CONFIG_MAX_MEM_MAPPED)
  265. *regs = &emif1_ddr3_532_mhz_1cs_2G;
  266. else
  267. *regs = &emif1_ddr3_532_mhz_1cs;
  268. break;
  269. case 2:
  270. if (ram_size > CONFIG_MAX_MEM_MAPPED)
  271. *regs = &emif2_ddr3_532_mhz_1cs_2G;
  272. else
  273. *regs = &emif2_ddr3_532_mhz_1cs;
  274. break;
  275. }
  276. break;
  277. case DRA762_ABZ_ES1_0:
  278. case DRA762_ACD_ES1_0:
  279. case DRA762_ES1_0:
  280. if (emif_nr == 1)
  281. *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra76;
  282. else
  283. *regs = &emif_2_regs_ddr3_666_mhz_1cs_dra76;
  284. break;
  285. case DRA722_ES1_0:
  286. case DRA722_ES2_0:
  287. case DRA722_ES2_1:
  288. if (ram_size < CONFIG_MAX_MEM_MAPPED)
  289. *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
  290. else
  291. *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2;
  292. break;
  293. default:
  294. *regs = &emif1_ddr3_532_mhz_1cs;
  295. }
  296. }
  297. static const struct dmm_lisa_map_regs lisa_map_dra7_1536MB = {
  298. .dmm_lisa_map_0 = 0x0,
  299. .dmm_lisa_map_1 = 0x80640300,
  300. .dmm_lisa_map_2 = 0xC0500220,
  301. .dmm_lisa_map_3 = 0xFF020100,
  302. .is_ma_present = 0x1
  303. };
  304. static const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
  305. .dmm_lisa_map_0 = 0x0,
  306. .dmm_lisa_map_1 = 0x0,
  307. .dmm_lisa_map_2 = 0x80600100,
  308. .dmm_lisa_map_3 = 0xFF020100,
  309. .is_ma_present = 0x1
  310. };
  311. const struct dmm_lisa_map_regs lisa_map_dra7_2GB = {
  312. .dmm_lisa_map_0 = 0x0,
  313. .dmm_lisa_map_1 = 0x0,
  314. .dmm_lisa_map_2 = 0x80740300,
  315. .dmm_lisa_map_3 = 0xFF020100,
  316. .is_ma_present = 0x1
  317. };
  318. /*
  319. * DRA722 EVM EMIF1 2GB CONFIGURATION
  320. * EMIF1 4 devices of 512Mb x 8 Micron
  321. */
  322. const struct dmm_lisa_map_regs lisa_map_2G_x_4 = {
  323. .dmm_lisa_map_0 = 0x0,
  324. .dmm_lisa_map_1 = 0x0,
  325. .dmm_lisa_map_2 = 0x80700100,
  326. .dmm_lisa_map_3 = 0xFF020100,
  327. .is_ma_present = 0x1
  328. };
  329. void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
  330. {
  331. u64 ram_size;
  332. ram_size = board_ti_get_emif_size();
  333. switch (omap_revision()) {
  334. case DRA762_ABZ_ES1_0:
  335. case DRA762_ACD_ES1_0:
  336. case DRA762_ES1_0:
  337. case DRA752_ES1_0:
  338. case DRA752_ES1_1:
  339. case DRA752_ES2_0:
  340. if (ram_size > CONFIG_MAX_MEM_MAPPED)
  341. *dmm_lisa_regs = &lisa_map_dra7_2GB;
  342. else
  343. *dmm_lisa_regs = &lisa_map_dra7_1536MB;
  344. break;
  345. case DRA722_ES1_0:
  346. case DRA722_ES2_0:
  347. case DRA722_ES2_1:
  348. default:
  349. if (ram_size < CONFIG_MAX_MEM_MAPPED)
  350. *dmm_lisa_regs = &lisa_map_2G_x_2;
  351. else
  352. *dmm_lisa_regs = &lisa_map_2G_x_4;
  353. break;
  354. }
  355. }
  356. struct vcores_data dra752_volts = {
  357. .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
  358. .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
  359. .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  360. .mpu.addr = TPS659038_REG_ADDR_SMPS12,
  361. .mpu.pmic = &tps659038,
  362. .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
  363. .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
  364. .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
  365. .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
  366. .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
  367. .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
  368. .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
  369. .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  370. .eve.addr = TPS659038_REG_ADDR_SMPS45,
  371. .eve.pmic = &tps659038,
  372. .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
  373. .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
  374. .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
  375. .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
  376. .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
  377. .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
  378. .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
  379. .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  380. .gpu.addr = TPS659038_REG_ADDR_SMPS6,
  381. .gpu.pmic = &tps659038,
  382. .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
  383. .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
  384. .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
  385. .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  386. .core.addr = TPS659038_REG_ADDR_SMPS7,
  387. .core.pmic = &tps659038,
  388. .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
  389. .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
  390. .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
  391. .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
  392. .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
  393. .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
  394. .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  395. .iva.addr = TPS659038_REG_ADDR_SMPS8,
  396. .iva.pmic = &tps659038,
  397. .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
  398. };
  399. struct vcores_data dra76x_volts = {
  400. .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
  401. .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
  402. .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  403. .mpu.addr = LP87565_REG_ADDR_BUCK01,
  404. .mpu.pmic = &lp87565,
  405. .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
  406. .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
  407. .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
  408. .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
  409. .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
  410. .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
  411. .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
  412. .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  413. .eve.addr = TPS65917_REG_ADDR_SMPS1,
  414. .eve.pmic = &tps659038,
  415. .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
  416. .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
  417. .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
  418. .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
  419. .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
  420. .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
  421. .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
  422. .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  423. .gpu.addr = LP87565_REG_ADDR_BUCK23,
  424. .gpu.pmic = &lp87565,
  425. .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
  426. .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
  427. .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
  428. .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  429. .core.addr = TPS65917_REG_ADDR_SMPS3,
  430. .core.pmic = &tps659038,
  431. .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
  432. .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
  433. .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
  434. .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
  435. .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
  436. .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
  437. .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  438. .iva.addr = TPS65917_REG_ADDR_SMPS4,
  439. .iva.pmic = &tps659038,
  440. .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
  441. };
  442. struct vcores_data dra722_volts = {
  443. .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
  444. .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
  445. .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  446. .mpu.addr = TPS65917_REG_ADDR_SMPS1,
  447. .mpu.pmic = &tps659038,
  448. .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
  449. .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
  450. .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
  451. .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  452. .core.addr = TPS65917_REG_ADDR_SMPS2,
  453. .core.pmic = &tps659038,
  454. /*
  455. * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
  456. * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
  457. */
  458. .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
  459. .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
  460. .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
  461. .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
  462. .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
  463. .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
  464. .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  465. .gpu.addr = TPS65917_REG_ADDR_SMPS3,
  466. .gpu.pmic = &tps659038,
  467. .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
  468. .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
  469. .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
  470. .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
  471. .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
  472. .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
  473. .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
  474. .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  475. .eve.addr = TPS65917_REG_ADDR_SMPS3,
  476. .eve.pmic = &tps659038,
  477. .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
  478. .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
  479. .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
  480. .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
  481. .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
  482. .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
  483. .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
  484. .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  485. .iva.addr = TPS65917_REG_ADDR_SMPS3,
  486. .iva.pmic = &tps659038,
  487. .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
  488. };
  489. struct vcores_data dra718_volts = {
  490. /*
  491. * In the case of dra71x GPU MPU and CORE
  492. * are all powered up by BUCK0 of LP873X PMIC
  493. */
  494. .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
  495. .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
  496. .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  497. .mpu.addr = LP873X_REG_ADDR_BUCK0,
  498. .mpu.pmic = &lp8733,
  499. .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
  500. .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
  501. .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
  502. .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  503. .core.addr = LP873X_REG_ADDR_BUCK0,
  504. .core.pmic = &lp8733,
  505. .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
  506. .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
  507. .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  508. .gpu.addr = LP873X_REG_ADDR_BUCK0,
  509. .gpu.pmic = &lp8733,
  510. .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
  511. /*
  512. * The DSPEVE and IVA rails are grouped on DRA71x-evm
  513. * and are powered by BUCK1 of LP873X PMIC
  514. */
  515. .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
  516. .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
  517. .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
  518. .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
  519. .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  520. .eve.addr = LP873X_REG_ADDR_BUCK1,
  521. .eve.pmic = &lp8733,
  522. .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
  523. .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
  524. .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
  525. .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
  526. .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
  527. .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  528. .iva.addr = LP873X_REG_ADDR_BUCK1,
  529. .iva.pmic = &lp8733,
  530. .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
  531. };
  532. int get_voltrail_opp(int rail_offset)
  533. {
  534. int opp;
  535. switch (rail_offset) {
  536. case VOLT_MPU:
  537. opp = DRA7_MPU_OPP;
  538. /* DRA71x supports only OPP_NOM for MPU */
  539. if (board_is_dra71x_evm())
  540. opp = OPP_NOM;
  541. break;
  542. case VOLT_CORE:
  543. opp = DRA7_CORE_OPP;
  544. /* DRA71x supports only OPP_NOM for CORE */
  545. if (board_is_dra71x_evm())
  546. opp = OPP_NOM;
  547. break;
  548. case VOLT_GPU:
  549. opp = DRA7_GPU_OPP;
  550. /* DRA71x supports only OPP_NOM for GPU */
  551. if (board_is_dra71x_evm())
  552. opp = OPP_NOM;
  553. break;
  554. case VOLT_EVE:
  555. opp = DRA7_DSPEVE_OPP;
  556. /*
  557. * DRA71x does not support OPP_OD for EVE.
  558. * If OPP_OD is selected by menuconfig, fallback
  559. * to OPP_NOM.
  560. */
  561. if (board_is_dra71x_evm() && opp == OPP_OD)
  562. opp = OPP_NOM;
  563. break;
  564. case VOLT_IVA:
  565. opp = DRA7_IVA_OPP;
  566. /*
  567. * DRA71x does not support OPP_OD for IVA.
  568. * If OPP_OD is selected by menuconfig, fallback
  569. * to OPP_NOM.
  570. */
  571. if (board_is_dra71x_evm() && opp == OPP_OD)
  572. opp = OPP_NOM;
  573. break;
  574. default:
  575. opp = OPP_NOM;
  576. }
  577. return opp;
  578. }
  579. /**
  580. * @brief board_init
  581. *
  582. * @return 0
  583. */
  584. int board_init(void)
  585. {
  586. gpmc_init();
  587. gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
  588. return 0;
  589. }
  590. int dram_init_banksize(void)
  591. {
  592. u64 ram_size;
  593. ram_size = board_ti_get_emif_size();
  594. gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  595. gd->bd->bi_dram[0].size = get_effective_memsize();
  596. if (ram_size > CONFIG_MAX_MEM_MAPPED) {
  597. gd->bd->bi_dram[1].start = 0x200000000;
  598. gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED;
  599. }
  600. return 0;
  601. }
  602. #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
  603. static int device_okay(const char *path)
  604. {
  605. int node;
  606. node = fdt_path_offset(gd->fdt_blob, path);
  607. if (node < 0)
  608. return 0;
  609. return fdtdec_get_is_enabled(gd->fdt_blob, node);
  610. }
  611. #endif
  612. int board_late_init(void)
  613. {
  614. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  615. char *name = "unknown";
  616. if (is_dra72x()) {
  617. if (board_is_dra72x_revc_or_later())
  618. name = "dra72x-revc";
  619. else if (board_is_dra71x_evm())
  620. name = "dra71x";
  621. else
  622. name = "dra72x";
  623. } else if (is_dra76x_abz()) {
  624. name = "dra76x_abz";
  625. } else if (is_dra76x_acd()) {
  626. name = "dra76x_acd";
  627. } else {
  628. name = "dra7xx";
  629. }
  630. set_board_info_env(name);
  631. /*
  632. * Default FIT boot on HS devices. Non FIT images are not allowed
  633. * on HS devices.
  634. */
  635. if (get_device_type() == HS_DEVICE)
  636. env_set("boot_fit", "1");
  637. omap_die_id_serial();
  638. omap_set_fastboot_vars();
  639. /*
  640. * Hook the LDO1 regulator to EN pin. This applies only to LP8733
  641. * Rest all regulators are hooked to EN Pin at reset.
  642. */
  643. if (board_is_dra71x_evm())
  644. palmas_i2c_write_u8(LP873X_I2C_SLAVE_ADDR, 0x9, 0x7);
  645. #endif
  646. #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
  647. if (device_okay("/ocp/omap_dwc3_1@48880000"))
  648. enable_usb_clocks(0);
  649. if (device_okay("/ocp/omap_dwc3_2@488c0000"))
  650. enable_usb_clocks(1);
  651. #endif
  652. return 0;
  653. }
  654. #ifdef CONFIG_SPL_BUILD
  655. void do_board_detect(void)
  656. {
  657. int rc;
  658. rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
  659. CONFIG_EEPROM_CHIP_ADDRESS);
  660. if (rc)
  661. printf("ti_i2c_eeprom_init failed %d\n", rc);
  662. }
  663. #else
  664. void do_board_detect(void)
  665. {
  666. char *bname = NULL;
  667. int rc;
  668. rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
  669. CONFIG_EEPROM_CHIP_ADDRESS);
  670. if (rc)
  671. printf("ti_i2c_eeprom_init failed %d\n", rc);
  672. if (board_is_dra74x_evm()) {
  673. bname = "DRA74x EVM";
  674. } else if (board_is_dra72x_evm()) {
  675. bname = "DRA72x EVM";
  676. } else if (board_is_dra71x_evm()) {
  677. bname = "DRA71x EVM";
  678. } else if (board_is_dra76x_evm()) {
  679. bname = "DRA76x EVM";
  680. } else {
  681. /* If EEPROM is not populated */
  682. if (is_dra72x())
  683. bname = "DRA72x EVM";
  684. else
  685. bname = "DRA74x EVM";
  686. }
  687. if (bname)
  688. snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
  689. "Board: %s REV %s\n", bname, board_ti_get_rev());
  690. }
  691. #endif /* CONFIG_SPL_BUILD */
  692. void vcores_init(void)
  693. {
  694. if (board_is_dra74x_evm()) {
  695. *omap_vcores = &dra752_volts;
  696. } else if (board_is_dra72x_evm()) {
  697. *omap_vcores = &dra722_volts;
  698. } else if (board_is_dra71x_evm()) {
  699. *omap_vcores = &dra718_volts;
  700. } else if (board_is_dra76x_evm()) {
  701. *omap_vcores = &dra76x_volts;
  702. } else {
  703. /* If EEPROM is not populated */
  704. if (is_dra72x())
  705. *omap_vcores = &dra722_volts;
  706. else
  707. *omap_vcores = &dra752_volts;
  708. }
  709. }
  710. void set_muxconf_regs(void)
  711. {
  712. do_set_mux32((*ctrl)->control_padconf_core_base,
  713. early_padconf, ARRAY_SIZE(early_padconf));
  714. }
  715. #if defined(CONFIG_MTD_RAW_NAND)
  716. static int nand_sw_detect(void)
  717. {
  718. int rc;
  719. uchar data[2];
  720. struct udevice *dev;
  721. rc = i2c_get_chip_for_busnum(NAND_PCF8575_I2C_BUS_NUM,
  722. NAND_PCF8575_ADDR, 0, &dev);
  723. if (rc)
  724. return -1;
  725. rc = dm_i2c_read(dev, 0, (uint8_t *)&data, sizeof(data));
  726. if (rc)
  727. return -1;
  728. /* We are only interested in P10 and P11 on PCF8575 which is equal to
  729. * bits 8 and 9.
  730. */
  731. data[1] = data[1] & 0x3;
  732. /* Ensure only P11 is set and P10 is cleared. This ensures only
  733. * NAND (P10) is configured and not NOR (P11) which are both low
  734. * true signals. NAND and NOR settings should not be enabled at
  735. * the same time.
  736. */
  737. if (data[1] == 0x2)
  738. return 0;
  739. return -1;
  740. }
  741. #else
  742. int nand_sw_detect(void)
  743. {
  744. return -1;
  745. }
  746. #endif
  747. #ifdef CONFIG_IODELAY_RECALIBRATION
  748. void recalibrate_iodelay(void)
  749. {
  750. struct pad_conf_entry const *pads, *delta_pads = NULL;
  751. struct iodelay_cfg_entry const *iodelay;
  752. int npads, niodelays, delta_npads = 0;
  753. int ret;
  754. switch (omap_revision()) {
  755. case DRA722_ES1_0:
  756. case DRA722_ES2_0:
  757. case DRA722_ES2_1:
  758. pads = dra72x_core_padconf_array_common;
  759. npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
  760. if (board_is_dra71x_evm()) {
  761. pads = dra71x_core_padconf_array;
  762. npads = ARRAY_SIZE(dra71x_core_padconf_array);
  763. iodelay = dra71_iodelay_cfg_array;
  764. niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array);
  765. /* If SW8 on the EVM is set to enable NAND then
  766. * overwrite the pins used by VOUT3 with NAND.
  767. */
  768. if (!nand_sw_detect()) {
  769. delta_pads = dra71x_nand_padconf_array;
  770. delta_npads =
  771. ARRAY_SIZE(dra71x_nand_padconf_array);
  772. } else {
  773. delta_pads = dra71x_vout3_padconf_array;
  774. delta_npads =
  775. ARRAY_SIZE(dra71x_vout3_padconf_array);
  776. }
  777. } else if (board_is_dra72x_revc_or_later()) {
  778. delta_pads = dra72x_rgmii_padconf_array_revc;
  779. delta_npads =
  780. ARRAY_SIZE(dra72x_rgmii_padconf_array_revc);
  781. iodelay = dra72_iodelay_cfg_array_revc;
  782. niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc);
  783. } else {
  784. delta_pads = dra72x_rgmii_padconf_array_revb;
  785. delta_npads =
  786. ARRAY_SIZE(dra72x_rgmii_padconf_array_revb);
  787. iodelay = dra72_iodelay_cfg_array_revb;
  788. niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb);
  789. }
  790. break;
  791. case DRA752_ES1_0:
  792. case DRA752_ES1_1:
  793. pads = dra74x_core_padconf_array;
  794. npads = ARRAY_SIZE(dra74x_core_padconf_array);
  795. iodelay = dra742_es1_1_iodelay_cfg_array;
  796. niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
  797. break;
  798. case DRA762_ACD_ES1_0:
  799. case DRA762_ES1_0:
  800. pads = dra76x_core_padconf_array;
  801. npads = ARRAY_SIZE(dra76x_core_padconf_array);
  802. iodelay = dra76x_es1_0_iodelay_cfg_array;
  803. niodelays = ARRAY_SIZE(dra76x_es1_0_iodelay_cfg_array);
  804. break;
  805. default:
  806. case DRA752_ES2_0:
  807. case DRA762_ABZ_ES1_0:
  808. pads = dra74x_core_padconf_array;
  809. npads = ARRAY_SIZE(dra74x_core_padconf_array);
  810. iodelay = dra742_es2_0_iodelay_cfg_array;
  811. niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
  812. /* Setup port1 and port2 for rgmii with 'no-id' mode */
  813. clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK |
  814. RGMII1_ID_MODE_N_MASK);
  815. break;
  816. }
  817. /* Setup I/O isolation */
  818. ret = __recalibrate_iodelay_start();
  819. if (ret)
  820. goto err;
  821. /* Do the muxing here */
  822. do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads);
  823. /* Now do the weird minor deltas that should be safe */
  824. if (delta_npads)
  825. do_set_mux32((*ctrl)->control_padconf_core_base,
  826. delta_pads, delta_npads);
  827. if (is_dra76x())
  828. /* Set mux for MCAN instead of DCAN1 */
  829. clrsetbits_le32((*ctrl)->control_core_control_spare_rw,
  830. MCAN_SEL_ALT_MASK, MCAN_SEL);
  831. /* Setup IOdelay configuration */
  832. ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
  833. err:
  834. /* Closeup.. remove isolation */
  835. __recalibrate_iodelay_end(ret);
  836. }
  837. #endif
  838. #if defined(CONFIG_MMC)
  839. int board_mmc_init(struct bd_info *bis)
  840. {
  841. omap_mmc_init(0, 0, 0, -1, -1);
  842. omap_mmc_init(1, 0, 0, -1, -1);
  843. return 0;
  844. }
  845. void board_mmc_poweron_ldo(uint voltage)
  846. {
  847. if (board_is_dra71x_evm()) {
  848. if (voltage == LDO_VOLT_3V0)
  849. voltage = 0x19;
  850. else if (voltage == LDO_VOLT_1V8)
  851. voltage = 0xa;
  852. lp873x_mmc1_poweron_ldo(voltage);
  853. } else if (board_is_dra76x_evm()) {
  854. palmas_mmc1_poweron_ldo(LDO4_VOLTAGE, LDO4_CTRL, voltage);
  855. } else {
  856. palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage);
  857. }
  858. }
  859. static const struct mmc_platform_fixups dra7x_es1_1_mmc1_fixups = {
  860. .hw_rev = "rev11",
  861. .unsupported_caps = MMC_CAP(MMC_HS_200) |
  862. MMC_CAP(UHS_SDR104),
  863. .max_freq = 96000000,
  864. };
  865. static const struct mmc_platform_fixups dra7x_es1_1_mmc23_fixups = {
  866. .hw_rev = "rev11",
  867. .unsupported_caps = MMC_CAP(MMC_HS_200) |
  868. MMC_CAP(UHS_SDR104) |
  869. MMC_CAP(UHS_SDR50),
  870. .max_freq = 48000000,
  871. };
  872. const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
  873. {
  874. switch (omap_revision()) {
  875. case DRA752_ES1_0:
  876. case DRA752_ES1_1:
  877. if (addr == OMAP_HSMMC1_BASE)
  878. return &dra7x_es1_1_mmc1_fixups;
  879. else
  880. return &dra7x_es1_1_mmc23_fixups;
  881. default:
  882. return NULL;
  883. }
  884. }
  885. #endif
  886. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
  887. int spl_start_uboot(void)
  888. {
  889. /* break into full u-boot on 'c' */
  890. if (serial_tstc() && serial_getc() == 'c')
  891. return 1;
  892. #ifdef CONFIG_SPL_ENV_SUPPORT
  893. env_init();
  894. env_load();
  895. if (env_get_yesno("boot_os") != 1)
  896. return 1;
  897. #endif
  898. return 0;
  899. }
  900. #endif
  901. #ifdef CONFIG_BOARD_EARLY_INIT_F
  902. /* VTT regulator enable */
  903. static inline void vtt_regulator_enable(void)
  904. {
  905. if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
  906. return;
  907. /* Do not enable VTT for DRA722 or DRA76x */
  908. if (is_dra72x() || is_dra76x())
  909. return;
  910. /*
  911. * EVM Rev G and later use gpio7_11 for DDR3 termination.
  912. * This is safe enough to do on older revs.
  913. */
  914. gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
  915. gpio_direction_output(GPIO_DDR_VTT_EN, 1);
  916. }
  917. int board_early_init_f(void)
  918. {
  919. vtt_regulator_enable();
  920. return 0;
  921. }
  922. #endif
  923. #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
  924. int ft_board_setup(void *blob, struct bd_info *bd)
  925. {
  926. ft_cpu_setup(blob, bd);
  927. return 0;
  928. }
  929. #endif
  930. #ifdef CONFIG_SPL_LOAD_FIT
  931. int board_fit_config_name_match(const char *name)
  932. {
  933. if (is_dra72x()) {
  934. if (board_is_dra71x_evm()) {
  935. if (!strcmp(name, "dra71-evm"))
  936. return 0;
  937. }else if(board_is_dra72x_revc_or_later()) {
  938. if (!strcmp(name, "dra72-evm-revc"))
  939. return 0;
  940. } else if (!strcmp(name, "dra72-evm")) {
  941. return 0;
  942. }
  943. } else if (is_dra76x_acd() && !strcmp(name, "dra76-evm")) {
  944. return 0;
  945. } else if (!is_dra72x() && !is_dra76x_acd() &&
  946. !strcmp(name, "dra7-evm")) {
  947. return 0;
  948. }
  949. return -1;
  950. }
  951. #endif
  952. #if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
  953. int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason)
  954. {
  955. if (reason != FASTBOOT_REBOOT_REASON_BOOTLOADER)
  956. return -ENOTSUPP;
  957. printf("Setting reboot to fastboot flag ...\n");
  958. env_set("dofastboot", "1");
  959. env_save();
  960. return 0;
  961. }
  962. #endif
  963. #ifdef CONFIG_TI_SECURE_DEVICE
  964. void board_fit_image_post_process(const void *fit, int node, void **p_image,
  965. size_t *p_size)
  966. {
  967. secure_boot_verify_image(p_image, p_size);
  968. }
  969. void board_tee_image_process(ulong tee_image, size_t tee_size)
  970. {
  971. secure_tee_install((u32)tee_image);
  972. }
  973. U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
  974. #endif