spl.c 3.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Technexion Ltd.
  4. *
  5. * Author: Richard Hu <richard.hu@technexion.com>
  6. */
  7. #include <common.h>
  8. #include <cpu_func.h>
  9. #include <init.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch/imx-regs.h>
  12. #include <asm/arch/crm_regs.h>
  13. #include <asm/arch/mx7-pins.h>
  14. #include <asm/arch/sys_proto.h>
  15. #include <asm/arch-mx7/mx7-ddr.h>
  16. #include <asm/mach-imx/iomux-v3.h>
  17. #include <asm/gpio.h>
  18. #include <fsl_esdhc_imx.h>
  19. #include <spl.h>
  20. #if defined(CONFIG_SPL_BUILD)
  21. #ifdef CONFIG_SPL_OS_BOOT
  22. int spl_start_uboot(void)
  23. {
  24. /* Break into full U-Boot on 'c' */
  25. if (serial_tstc() && serial_getc() == 'c')
  26. return 1;
  27. return 0;
  28. }
  29. #endif
  30. static struct ddrc ddrc_regs_val = {
  31. .mstr = 0x01040001,
  32. .rfshtmg = 0x00400046,
  33. .init1 = 0x00690000,
  34. .init0 = 0x00020083,
  35. .init3 = 0x09300004,
  36. .init4 = 0x04080000,
  37. .init5 = 0x00100004,
  38. .rankctl = 0x0000033F,
  39. .dramtmg0 = 0x09081109,
  40. .dramtmg1 = 0x0007020d,
  41. .dramtmg2 = 0x03040407,
  42. .dramtmg3 = 0x00002006,
  43. .dramtmg4 = 0x04020205,
  44. .dramtmg5 = 0x03030202,
  45. .dramtmg8 = 0x00000803,
  46. .zqctl0 = 0x00800020,
  47. .dfitmg0 = 0x02098204,
  48. .dfitmg1 = 0x00030303,
  49. .dfiupd0 = 0x80400003,
  50. .dfiupd1 = 0x00100020,
  51. .dfiupd2 = 0x80100004,
  52. .addrmap4 = 0x00000F0F,
  53. .odtcfg = 0x06000604,
  54. .odtmap = 0x00000001,
  55. .rfshtmg = 0x00400046,
  56. .dramtmg0 = 0x09081109,
  57. .addrmap0 = 0x0000001f,
  58. .addrmap1 = 0x00080808,
  59. .addrmap4 = 0x00000f0f,
  60. .addrmap5 = 0x07070707,
  61. .addrmap6 = 0x0f0f0707,
  62. };
  63. static struct ddrc_mp ddrc_mp_val = {
  64. .pctrl_0 = 0x00000001,
  65. };
  66. static struct ddr_phy ddr_phy_regs_val = {
  67. .phy_con0 = 0x17420f40,
  68. .phy_con1 = 0x10210100,
  69. .phy_con4 = 0x00060807,
  70. .mdll_con0 = 0x1010007e,
  71. .drvds_con0 = 0x00000d6e,
  72. .cmd_sdll_con0 = 0x00000010,
  73. .offset_lp_con0 = 0x0000000f,
  74. .offset_rd_con0 = 0x08080808,
  75. .offset_wr_con0 = 0x08080808,
  76. };
  77. static struct mx7_calibration calib_param = {
  78. .num_val = 5,
  79. .values = {
  80. 0x0E407304,
  81. 0x0E447304,
  82. 0x0E447306,
  83. 0x0E447304,
  84. 0x0E447304,
  85. },
  86. };
  87. static void gpr_init(void)
  88. {
  89. struct iomuxc_gpr_base_regs *gpr_regs =
  90. (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  91. writel(0x4F400005, &gpr_regs->gpr[1]);
  92. }
  93. static bool is_1g(void)
  94. {
  95. gpio_direction_input(IMX_GPIO_NR(1, 12));
  96. return !gpio_get_value(IMX_GPIO_NR(1, 12));
  97. }
  98. static void ddr_init(void)
  99. {
  100. if (is_1g())
  101. ddrc_regs_val.addrmap6 = 0x0f070707;
  102. mx7_dram_cfg(&ddrc_regs_val, &ddrc_mp_val, &ddr_phy_regs_val,
  103. &calib_param);
  104. }
  105. void board_init_f(ulong dummy)
  106. {
  107. arch_cpu_init();
  108. gpr_init();
  109. board_early_init_f();
  110. timer_init();
  111. preloader_console_init();
  112. ddr_init();
  113. memset(__bss_start, 0, __bss_end - __bss_start);
  114. board_init_r(NULL, 0);
  115. }
  116. void reset_cpu(void)
  117. {
  118. }
  119. #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
  120. PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
  121. static iomux_v3_cfg_t const usdhc3_pads[] = {
  122. MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  123. MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  124. MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  125. MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  126. MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  127. MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  128. MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  129. MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  130. MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  131. MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  132. MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  133. };
  134. static struct fsl_esdhc_cfg usdhc_cfg[1] = {
  135. {USDHC3_BASE_ADDR},
  136. };
  137. int board_mmc_getcd(struct mmc *mmc)
  138. {
  139. /* Assume uSDHC3 emmc is always present */
  140. return 1;
  141. }
  142. int board_mmc_init(struct bd_info *bis)
  143. {
  144. imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  145. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  146. return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  147. }
  148. #endif