iot_devkit.c 4.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <init.h>
  8. #include <malloc.h>
  9. #include <dwmmc.h>
  10. #include <asm/global_data.h>
  11. #include <linux/bitops.h>
  12. #include <linux/libfdt.h>
  13. #include <fdtdec.h>
  14. #include <asm/arcregs.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. #define SYSCON_BASE 0xf000a000
  17. #define AHBCKDIV (void *)(SYSCON_BASE + 0x04)
  18. #define APBCKDIV (void *)(SYSCON_BASE + 0x08)
  19. #define APBCKEN (void *)(SYSCON_BASE + 0x0C)
  20. #define RESET_REG (void *)(SYSCON_BASE + 0x18)
  21. #define CLKSEL (void *)(SYSCON_BASE + 0x24)
  22. #define CLKSTAT (void *)(SYSCON_BASE + 0x28)
  23. #define PLLCON (void *)(SYSCON_BASE + 0x2C)
  24. #define APBCKSEL (void *)(SYSCON_BASE + 0x30)
  25. #define AHBCKEN (void *)(SYSCON_BASE + 0x34)
  26. #define USBPHY_PLL (void *)(SYSCON_BASE + 0x78)
  27. #define USBCFG (void *)(SYSCON_BASE + 0x7c)
  28. #define PLL_MASK_0 0xffcfffff
  29. #define PLL_MASK_1 0xffcfff00
  30. #define PLL_MASK_2 0xfbcfff00
  31. #define CLKSEL_DEFAULT 0x5a690000
  32. static int set_cpu_freq(unsigned int clk)
  33. {
  34. clk /= 1000000;
  35. /* Set clk to ext Xtal (LSN value 0) */
  36. writel(CLKSEL_DEFAULT, CLKSEL);
  37. switch (clk) {
  38. case 16:
  39. /* Bypass mode */
  40. return 0;
  41. case 50:
  42. writel(readl(PLLCON) & PLL_MASK_0, PLLCON);
  43. /* pll_off=1, M=25, N=1, OD=3, PLL_OUT_CLK=50M */
  44. writel((readl(PLLCON) & PLL_MASK_1) | 0x300191, PLLCON);
  45. /* pll_off=0, M=25, N=1, OD=3, PLL_OUT_CLK=50M */
  46. writel((readl(PLLCON) & PLL_MASK_2) | 0x300191, PLLCON);
  47. break;
  48. case 72:
  49. writel(readl(PLLCON) & PLL_MASK_0, PLLCON);
  50. /* pll_off=1, M=18, N=1, OD=2, PLL_OUT_CLK=72M */
  51. writel((readl(PLLCON) & PLL_MASK_1) | 0x200121, PLLCON);
  52. /* pll_off=0, M=18, N=1, OD=2, PLL_OUT_CLK=72M */
  53. writel((readl(PLLCON) & PLL_MASK_2) | 0x200121, PLLCON);
  54. break;
  55. case 100:
  56. writel(readl(PLLCON) & PLL_MASK_0, PLLCON);
  57. /* pll_off=1,M=25, N=1, OD=2, PLL_OUT_CLK=100M */
  58. writel((readl(PLLCON) & PLL_MASK_1) | 0x200191, PLLCON);
  59. /* pll_off=0,M=25, N=1, OD=2, PLL_OUT_CLK=100M */
  60. writel((readl(PLLCON) & PLL_MASK_2) | 0x200191, PLLCON);
  61. break;
  62. case 136:
  63. writel(readl(PLLCON) & PLL_MASK_0, PLLCON);
  64. /* pll_off=1, M=17, N=1, OD=1, PLL_OUT_CLK=136M */
  65. writel((readl(PLLCON) & PLL_MASK_1) | 0x100111, PLLCON);
  66. /* pll_off=0, M=17, N=1, OD=1, PLL_OUT_CLK=136M */
  67. writel((readl(PLLCON) & PLL_MASK_2) | 0x100111, PLLCON);
  68. break;
  69. case 144:
  70. writel(readl(PLLCON) & PLL_MASK_0, PLLCON);
  71. /* pll_off=1, M=18, N=1, OD=1, PLL_OUT_CLK=144M */
  72. writel((readl(PLLCON) & PLL_MASK_1) | 0x100121, PLLCON);
  73. /* pll_off=0, M=18, N=1, OD=1, PLL_OUT_CLK=144M */
  74. writel((readl(PLLCON) & PLL_MASK_2) | 0x100121, PLLCON);
  75. break;
  76. default:
  77. return -EINVAL;
  78. }
  79. while (!(readl(CLKSTAT) & 0x4))
  80. ;
  81. /* Set clk from PLL on bus (LSN = 1) */
  82. writel(CLKSEL_DEFAULT | BIT(0), CLKSEL);
  83. return 0;
  84. }
  85. extern u8 __rom_end[];
  86. extern u8 __ram_start[];
  87. extern u8 __ram_end[];
  88. /*
  89. * Use mach_cpu_init() for .data section copy as board_early_init_f() will be
  90. * too late: initf_dm() will use a value of "av_" variable from not yet
  91. * initialized (by copy) area.
  92. */
  93. int mach_cpu_init(void)
  94. {
  95. int offset;
  96. /* Don't relocate U-Boot */
  97. gd->flags |= GD_FLG_SKIP_RELOC;
  98. /* Copy data from ROM to RAM */
  99. u8 *src = __rom_end;
  100. u8 *dst = __ram_start;
  101. while (dst < __ram_end)
  102. *dst++ = *src++;
  103. /* Enable debug uart */
  104. #define DEBUG_UART_BASE 0x80014000
  105. #define DEBUG_UART_DLF_OFFSET 0xc0
  106. write_aux_reg(DEBUG_UART_BASE + DEBUG_UART_DLF_OFFSET, 1);
  107. offset = fdt_path_offset(gd->fdt_blob, "/cpu_card/core_clk");
  108. if (offset < 0)
  109. return offset;
  110. gd->cpu_clk = fdtdec_get_int(gd->fdt_blob, offset, "clock-frequency", 0);
  111. if (!gd->cpu_clk)
  112. return -EINVAL;
  113. /* If CPU freq > 100 MHz, divide eFLASH clock by 2 */
  114. if (gd->cpu_clk > 100000000) {
  115. u32 reg = readl(AHBCKDIV);
  116. reg &= ~(0xF << 8);
  117. reg |= 2 << 8;
  118. writel(reg, AHBCKDIV);
  119. }
  120. return set_cpu_freq(gd->cpu_clk);
  121. }
  122. #define IOTDK_RESET_SEQ 0x55AA6699
  123. void reset_cpu(void)
  124. {
  125. writel(IOTDK_RESET_SEQ, RESET_REG);
  126. }
  127. int checkboard(void)
  128. {
  129. puts("Board: Synopsys IoT Development Kit\n");
  130. return 0;
  131. };