dram_timings_sun4i.h 5.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205
  1. /* This file is automatically generated, do not edit */
  2. #if defined(CONFIG_DRAM_TIMINGS_DDR3_1066F_1333H)
  3. # if CONFIG_DRAM_CLK <= 360 /* DDR3-1066F @360MHz, timings: 6-5-5-14 */
  4. .cas = 6,
  5. .tpr0 = 0x268e5590,
  6. .tpr1 = 0xa090,
  7. .tpr2 = 0x22a00,
  8. .emr2 = 0x0,
  9. # elif CONFIG_DRAM_CLK <= 384 /* DDR3-1066F @384MHz, timings: 6-6-6-15 */
  10. .cas = 6,
  11. .tpr0 = 0x288f6690,
  12. .tpr1 = 0xa0a0,
  13. .tpr2 = 0x22a00,
  14. .emr2 = 0x0,
  15. # elif CONFIG_DRAM_CLK <= 396 /* DDR3-1066F @396MHz, timings: 6-6-6-15 */
  16. .cas = 6,
  17. .tpr0 = 0x2a8f6690,
  18. .tpr1 = 0xa0a0,
  19. .tpr2 = 0x22a00,
  20. .emr2 = 0x0,
  21. # elif CONFIG_DRAM_CLK <= 408 /* DDR3-1066F @408MHz, timings: 7-6-6-16 */
  22. .cas = 7,
  23. .tpr0 = 0x2ab06690,
  24. .tpr1 = 0xa0a8,
  25. .tpr2 = 0x22a00,
  26. .emr2 = 0x8,
  27. # elif CONFIG_DRAM_CLK <= 432 /* DDR3-1066F @432MHz, timings: 7-6-6-17 */
  28. .cas = 7,
  29. .tpr0 = 0x2cb16690,
  30. .tpr1 = 0xa0b0,
  31. .tpr2 = 0x22e00,
  32. .emr2 = 0x8,
  33. # elif CONFIG_DRAM_CLK <= 456 /* DDR3-1066F @456MHz, timings: 7-6-6-18 */
  34. .cas = 7,
  35. .tpr0 = 0x30b26690,
  36. .tpr1 = 0xa0b8,
  37. .tpr2 = 0x22e00,
  38. .emr2 = 0x8,
  39. # elif CONFIG_DRAM_CLK <= 468 /* DDR3-1066F @468MHz, timings: 7-7-7-18 */
  40. .cas = 7,
  41. .tpr0 = 0x30b27790,
  42. .tpr1 = 0xa0c0,
  43. .tpr2 = 0x23200,
  44. .emr2 = 0x8,
  45. # elif CONFIG_DRAM_CLK <= 480 /* DDR3-1066F @480MHz, timings: 7-7-7-18 */
  46. .cas = 7,
  47. .tpr0 = 0x32b27790,
  48. .tpr1 = 0xa0c0,
  49. .tpr2 = 0x23200,
  50. .emr2 = 0x8,
  51. # elif CONFIG_DRAM_CLK <= 504 /* DDR3-1066F @504MHz, timings: 7-7-7-19 */
  52. .cas = 7,
  53. .tpr0 = 0x34d37790,
  54. .tpr1 = 0xa0d0,
  55. .tpr2 = 0x23600,
  56. .emr2 = 0x8,
  57. # elif CONFIG_DRAM_CLK <= 528 /* DDR3-1066F @528MHz, timings: 7-7-7-20 */
  58. .cas = 7,
  59. .tpr0 = 0x36d47790,
  60. .tpr1 = 0xa0d8,
  61. .tpr2 = 0x23600,
  62. .emr2 = 0x8,
  63. # elif CONFIG_DRAM_CLK <= 540 /* DDR3-1333H @540MHz, timings: 9-8-8-20 */
  64. .cas = 9,
  65. .tpr0 = 0x36b488b4,
  66. .tpr1 = 0xa0c8,
  67. .tpr2 = 0x2b600,
  68. .emr2 = 0x10,
  69. # elif CONFIG_DRAM_CLK <= 552 /* DDR3-1333H @552MHz, timings: 9-8-8-20 */
  70. .cas = 9,
  71. .tpr0 = 0x38b488b4,
  72. .tpr1 = 0xa0c8,
  73. .tpr2 = 0x2ba00,
  74. .emr2 = 0x10,
  75. # elif CONFIG_DRAM_CLK <= 576 /* DDR3-1333H @576MHz, timings: 9-8-8-21 */
  76. .cas = 9,
  77. .tpr0 = 0x3ab588b4,
  78. .tpr1 = 0xa0d0,
  79. .tpr2 = 0x2ba00,
  80. .emr2 = 0x10,
  81. # elif CONFIG_DRAM_CLK <= 600 /* DDR3-1333H @600MHz, timings: 9-9-9-22 */
  82. .cas = 9,
  83. .tpr0 = 0x3cb699b4,
  84. .tpr1 = 0xa0d8,
  85. .tpr2 = 0x2be00,
  86. .emr2 = 0x10,
  87. # elif CONFIG_DRAM_CLK <= 624 /* DDR3-1333H @624MHz, timings: 9-9-9-23 */
  88. .cas = 9,
  89. .tpr0 = 0x3eb799b4,
  90. .tpr1 = 0xa0e8,
  91. .tpr2 = 0x2be00,
  92. .emr2 = 0x10,
  93. # elif CONFIG_DRAM_CLK <= 648 /* DDR3-1333H @648MHz, timings: 9-9-9-24 */
  94. .cas = 9,
  95. .tpr0 = 0x42b899b4,
  96. .tpr1 = 0xa0f0,
  97. .tpr2 = 0x2c200,
  98. .emr2 = 0x10,
  99. # else
  100. # error CONFIG_DRAM_CLK is set too high
  101. # endif
  102. #elif defined(CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J)
  103. # if CONFIG_DRAM_CLK <= 360 /* DDR3-800E @360MHz, timings: 6-6-6-14 */
  104. .cas = 6,
  105. .tpr0 = 0x268e6690,
  106. .tpr1 = 0xa090,
  107. .tpr2 = 0x22a00,
  108. .emr2 = 0x0,
  109. # elif CONFIG_DRAM_CLK <= 384 /* DDR3-800E @384MHz, timings: 6-6-6-15 */
  110. .cas = 6,
  111. .tpr0 = 0x2a8f6690,
  112. .tpr1 = 0xa0a0,
  113. .tpr2 = 0x22a00,
  114. .emr2 = 0x0,
  115. # elif CONFIG_DRAM_CLK <= 396 /* DDR3-800E @396MHz, timings: 6-6-6-15 */
  116. .cas = 6,
  117. .tpr0 = 0x2a8f6690,
  118. .tpr1 = 0xa0a0,
  119. .tpr2 = 0x22a00,
  120. .emr2 = 0x0,
  121. # elif CONFIG_DRAM_CLK <= 408 /* DDR3-1066G @408MHz, timings: 8-7-7-16 */
  122. .cas = 8,
  123. .tpr0 = 0x2cb07790,
  124. .tpr1 = 0xa0a8,
  125. .tpr2 = 0x22a00,
  126. .emr2 = 0x8,
  127. # elif CONFIG_DRAM_CLK <= 432 /* DDR3-1066G @432MHz, timings: 8-7-7-17 */
  128. .cas = 8,
  129. .tpr0 = 0x2eb17790,
  130. .tpr1 = 0xa0b0,
  131. .tpr2 = 0x22e00,
  132. .emr2 = 0x8,
  133. # elif CONFIG_DRAM_CLK <= 456 /* DDR3-1066G @456MHz, timings: 8-7-7-18 */
  134. .cas = 8,
  135. .tpr0 = 0x30b27790,
  136. .tpr1 = 0xa0b8,
  137. .tpr2 = 0x22e00,
  138. .emr2 = 0x8,
  139. # elif CONFIG_DRAM_CLK <= 468 /* DDR3-1066G @468MHz, timings: 8-8-8-18 */
  140. .cas = 8,
  141. .tpr0 = 0x32b28890,
  142. .tpr1 = 0xa0c0,
  143. .tpr2 = 0x23200,
  144. .emr2 = 0x8,
  145. # elif CONFIG_DRAM_CLK <= 480 /* DDR3-1066G @480MHz, timings: 8-8-8-18 */
  146. .cas = 8,
  147. .tpr0 = 0x34b28890,
  148. .tpr1 = 0xa0c0,
  149. .tpr2 = 0x23200,
  150. .emr2 = 0x8,
  151. # elif CONFIG_DRAM_CLK <= 504 /* DDR3-1066G @504MHz, timings: 8-8-8-19 */
  152. .cas = 8,
  153. .tpr0 = 0x36d38890,
  154. .tpr1 = 0xa0d0,
  155. .tpr2 = 0x23600,
  156. .emr2 = 0x8,
  157. # elif CONFIG_DRAM_CLK <= 528 /* DDR3-1066G @528MHz, timings: 8-8-8-20 */
  158. .cas = 8,
  159. .tpr0 = 0x38d48890,
  160. .tpr1 = 0xa0d8,
  161. .tpr2 = 0x23600,
  162. .emr2 = 0x8,
  163. # elif CONFIG_DRAM_CLK <= 540 /* DDR3-1333J @540MHz, timings: 10-9-9-20 */
  164. .cas = 10,
  165. .tpr0 = 0x38b499b4,
  166. .tpr1 = 0xa0c8,
  167. .tpr2 = 0x2b600,
  168. .emr2 = 0x10,
  169. # elif CONFIG_DRAM_CLK <= 552 /* DDR3-1333J @552MHz, timings: 10-9-9-20 */
  170. .cas = 10,
  171. .tpr0 = 0x3ab499b4,
  172. .tpr1 = 0xa0c8,
  173. .tpr2 = 0x2ba00,
  174. .emr2 = 0x10,
  175. # elif CONFIG_DRAM_CLK <= 576 /* DDR3-1333J @576MHz, timings: 10-9-9-21 */
  176. .cas = 10,
  177. .tpr0 = 0x3cb599b4,
  178. .tpr1 = 0xa0d0,
  179. .tpr2 = 0x2ba00,
  180. .emr2 = 0x10,
  181. # elif CONFIG_DRAM_CLK <= 600 /* DDR3-1333J @600MHz, timings: 10-9-9-22 */
  182. .cas = 10,
  183. .tpr0 = 0x3eb699b4,
  184. .tpr1 = 0xa0d8,
  185. .tpr2 = 0x2be00,
  186. .emr2 = 0x10,
  187. # elif CONFIG_DRAM_CLK <= 624 /* DDR3-1333J @624MHz, timings: 10-10-10-23 */
  188. .cas = 10,
  189. .tpr0 = 0x40b7aab4,
  190. .tpr1 = 0xa0e8,
  191. .tpr2 = 0x2be00,
  192. .emr2 = 0x10,
  193. # elif CONFIG_DRAM_CLK <= 648 /* DDR3-1333J @648MHz, timings: 10-10-10-24 */
  194. .cas = 10,
  195. .tpr0 = 0x44b8aab4,
  196. .tpr1 = 0xa0f0,
  197. .tpr2 = 0x2c200,
  198. .emr2 = 0x10,
  199. # else
  200. # error CONFIG_DRAM_CLK is set too high
  201. # endif
  202. #else
  203. # error CONFIG_DRAM_TIMINGS_* is not defined
  204. #endif