starfive_visionfive2.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2022 Starfive, Inc.
  4. * Author: yanhong <yanhong.wang@starfivetech.com>
  5. *
  6. */
  7. #include <common.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/eeprom.h>
  10. #include <asm/arch/jh7110-regs.h>
  11. #include <cpu_func.h>
  12. #include <dm/uclass.h>
  13. #include <dm/device.h>
  14. #include <env.h>
  15. #include <inttypes.h>
  16. #include <misc.h>
  17. #include <linux/bitops.h>
  18. #include <asm/arch/gpio.h>
  19. #include <bmp_logo.h>
  20. #include <video.h>
  21. #include <splash.h>
  22. #define SYS_CLOCK_ENABLE(clk) \
  23. setbits_le32(SYS_CRG_BASE + clk, CLK_ENABLE_MASK)
  24. #define PCB_REVISION_MASK 0xF0
  25. #define PCB_REVISION_SHIFT 4
  26. #define PCB_REVISION_A 0x0A
  27. #define PCB_REVISION_B 0x0B
  28. #define CHIP_REVISION_SHIFT 80
  29. #define CPU_VOL_BINNING_OFFSET 0x7fc
  30. DECLARE_GLOBAL_DATA_PTR;
  31. enum {
  32. BOOT_FLASH = 0,
  33. BOOT_SD,
  34. BOOT_EMMC,
  35. BOOT_UART,
  36. };
  37. enum chip_type_t {
  38. CHIP_A = 0,
  39. CHIP_B,
  40. CHIP_MAX,
  41. };
  42. enum board_type_t {
  43. BOARD_1000M_1000M = 0,
  44. BOARD_1000M_100M,
  45. BOARD_TYPE_MAX,
  46. };
  47. enum cpu_voltage_type_t {
  48. CPU_VOL_1020 = 0xef0,
  49. CPU_VOL_1040 = 0xfff,
  50. CPU_VOL_1060 = 0xff0,
  51. CPU_VOL_1000 = 0x8f0,
  52. };
  53. #define CPU_VOL_MASK 0xfff
  54. static void sys_reset_clear(ulong assert, ulong status, u32 rst)
  55. {
  56. u32 value;
  57. clrbits_le32(SYS_CRG_BASE + assert, BIT(rst));
  58. do {
  59. value = in_le32(SYS_CRG_BASE + status);
  60. } while ((value & BIT(rst)) != BIT(rst));
  61. }
  62. static void jh7110_timer_init(void)
  63. {
  64. SYS_CLOCK_ENABLE(TIMER_CLK_APB_SHIFT);
  65. SYS_CLOCK_ENABLE(TIMER_CLK_TIMER0_SHIFT);
  66. SYS_CLOCK_ENABLE(TIMER_CLK_TIMER1_SHIFT);
  67. SYS_CLOCK_ENABLE(TIMER_CLK_TIMER2_SHIFT);
  68. SYS_CLOCK_ENABLE(TIMER_CLK_TIMER3_SHIFT);
  69. sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
  70. SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_APB_SHIFT);
  71. sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
  72. SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER0_SHIFT);
  73. sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
  74. SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER1_SHIFT);
  75. sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
  76. SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER2_SHIFT);
  77. sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
  78. SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER3_SHIFT);
  79. }
  80. static void jh7110_gmac_init_1000M(int id)
  81. {
  82. switch (id) {
  83. case 0:
  84. clrsetbits_le32(AON_SYSCON_BASE + AON_SYSCFG_12,
  85. GMAC5_0_SEL_I_MASK,
  86. BIT(GMAC5_0_SEL_I_SHIFT) & GMAC5_0_SEL_I_MASK);
  87. break;
  88. case 1:
  89. clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_144,
  90. GMAC5_1_SEL_I_MASK,
  91. BIT(GMAC5_1_SEL_I_SHIFT) & GMAC5_1_SEL_I_MASK);
  92. break;
  93. default:
  94. break;
  95. }
  96. }
  97. static void jh7110_gmac_init_100M(int id)
  98. {
  99. switch (id) {
  100. case 0:
  101. clrsetbits_le32(AON_SYSCON_BASE + AON_SYSCFG_12,
  102. GMAC5_0_SEL_I_MASK,
  103. (4 << GMAC5_0_SEL_I_SHIFT) & GMAC5_0_SEL_I_MASK);
  104. setbits_le32(AON_CRG_BASE + GMAC5_0_CLK_TX_SHIFT, 0x1000000);
  105. setbits_le32(AON_CRG_BASE + GMAC5_0_CLK_RX_SHIFT, 0x1000000);
  106. break;
  107. case 1:
  108. clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_144,
  109. GMAC5_1_SEL_I_MASK,
  110. (4 << GMAC5_1_SEL_I_SHIFT) & GMAC5_1_SEL_I_MASK);
  111. setbits_le32(SYS_CRG_BASE + GMAC5_1_CLK_TX_SHIFT, 0x1000000);
  112. setbits_le32(SYS_CRG_BASE + GMAC5_1_CLK_RX_SHIFT, 0x1000000);
  113. break;
  114. default:
  115. break;
  116. }
  117. }
  118. static void jh7110_gmac_sel_tx_to_rgmii(int id)
  119. {
  120. switch (id) {
  121. case 0:
  122. clrsetbits_le32(AON_CRG_BASE + GMAC5_0_CLK_TX_SHIFT,
  123. GMAC5_0_CLK_TX_MASK,
  124. BIT(GMAC5_0_CLK_TX_BIT) & GMAC5_0_CLK_TX_MASK);
  125. break;
  126. case 1:
  127. clrsetbits_le32(SYS_CRG_BASE + GMAC5_1_CLK_TX_SHIFT,
  128. GMAC5_1_CLK_TX_MASK,
  129. BIT(GMAC5_1_CLK_TX_BIT) & GMAC5_1_CLK_TX_MASK);
  130. break;
  131. default:
  132. break;
  133. }
  134. }
  135. static void set_uboot_fdt_addr_env(void)
  136. {
  137. char str[17];
  138. ulong fdt_addr = (ulong)gd->fdt_blob;
  139. sprintf(str, "0x%lx", fdt_addr);
  140. env_set("uboot_fdt_addr", str);
  141. }
  142. static int get_chip_type(void)
  143. {
  144. int type;
  145. int len = -1;
  146. u8 data;
  147. len = get_data_from_eeprom(CHIP_REVISION_SHIFT, 1, &data);
  148. if (len <= 0) {
  149. env_set("chip_vision", "UNKOWN");
  150. return -EINVAL;
  151. }
  152. switch (data) {
  153. case 'a':
  154. case 'A':
  155. type = CHIP_A;
  156. env_set("chip_vision", "A");
  157. break;
  158. case 'b':
  159. case 'B':
  160. type = CHIP_B;
  161. env_set("chip_vision", "B");
  162. break;
  163. default:
  164. type = CHIP_MAX;
  165. env_set("chip_vision", "UNKOWN");
  166. break;
  167. }
  168. return type;
  169. }
  170. static int get_board_type(void)
  171. {
  172. u8 pv;
  173. int type;
  174. pv = get_pcb_revision_from_eeprom();
  175. pv = (pv & PCB_REVISION_MASK) >> PCB_REVISION_SHIFT;
  176. if (pv == PCB_REVISION_A) {
  177. type = BOARD_1000M_100M;
  178. } else if (pv == PCB_REVISION_B) {
  179. type = BOARD_1000M_1000M;
  180. } else {
  181. type = BOARD_TYPE_MAX;
  182. }
  183. return type;
  184. }
  185. static void jh7110_gmac_init(int chip_type, int pcb_type)
  186. {
  187. switch (chip_type) {
  188. case CHIP_A:
  189. break;
  190. case CHIP_B:
  191. default:
  192. jh7110_gmac_sel_tx_to_rgmii(0);
  193. jh7110_gmac_sel_tx_to_rgmii(1);
  194. break;
  195. }
  196. switch (pcb_type) {
  197. case BOARD_1000M_100M:
  198. jh7110_gmac_init_1000M(0);
  199. jh7110_gmac_init_100M(1);
  200. break;
  201. case BOARD_1000M_1000M:
  202. default:
  203. jh7110_gmac_init_1000M(0);
  204. jh7110_gmac_init_1000M(1);
  205. break;
  206. }
  207. }
  208. static void jh7110_usb_init(bool usb2_enable)
  209. {
  210. if (usb2_enable) {
  211. /*usb 2.0 utmi phy init*/
  212. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
  213. USB_MODE_STRAP_MASK,
  214. (2<<USB_MODE_STRAP_SHIFT) &
  215. USB_MODE_STRAP_MASK);/*2:host mode, 4:device mode*/
  216. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
  217. USB_OTG_SUSPENDM_BYPS_MASK,
  218. BIT(USB_OTG_SUSPENDM_BYPS_SHIFT)
  219. & USB_OTG_SUSPENDM_BYPS_MASK);
  220. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
  221. USB_OTG_SUSPENDM_MASK,
  222. BIT(USB_OTG_SUSPENDM_SHIFT) &
  223. USB_OTG_SUSPENDM_MASK);/*HOST = 1. DEVICE = 0;*/
  224. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
  225. USB_PLL_EN_MASK,
  226. BIT(USB_PLL_EN_SHIFT) & USB_PLL_EN_MASK);
  227. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
  228. USB_REFCLK_MODE_MASK,
  229. BIT(USB_REFCLK_MODE_SHIFT) & USB_REFCLK_MODE_MASK);
  230. /* usb 2.0 phy mode,REPLACE USB3.0 PHY module = 1;else = 0*/
  231. clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_24,
  232. PDRSTN_SPLIT_MASK,
  233. BIT(PDRSTN_SPLIT_SHIFT) &
  234. PDRSTN_SPLIT_MASK);
  235. } else {
  236. /*usb 3.0 pipe phy config*/
  237. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_196,
  238. PCIE_CKREF_SRC_MASK,
  239. (0<<PCIE_CKREF_SRC_SHIFT) & PCIE_CKREF_SRC_MASK);
  240. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_196,
  241. PCIE_CLK_SEL_MASK,
  242. (0<<PCIE_CLK_SEL_SHIFT) & PCIE_CLK_SEL_MASK);
  243. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_328,
  244. PCIE_PHY_MODE_MASK,
  245. BIT(PCIE_PHY_MODE_SHIFT) & PCIE_PHY_MODE_MASK);
  246. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_500,
  247. PCIE_USB3_BUS_WIDTH_MASK,
  248. (0 << PCIE_USB3_BUS_WIDTH_SHIFT) &
  249. PCIE_USB3_BUS_WIDTH_MASK);
  250. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_500,
  251. PCIE_USB3_RATE_MASK,
  252. (0 << PCIE_USB3_RATE_SHIFT) & PCIE_USB3_RATE_MASK);
  253. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_500,
  254. PCIE_USB3_RX_STANDBY_MASK,
  255. (0 << PCIE_USB3_RX_STANDBY_SHIFT)
  256. & PCIE_USB3_RX_STANDBY_MASK);
  257. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_500,
  258. PCIE_USB3_PHY_ENABLE_MASK,
  259. BIT(PCIE_USB3_PHY_ENABLE_SHIFT)
  260. & PCIE_USB3_PHY_ENABLE_MASK);
  261. /* usb 3.0 phy mode,REPLACE USB3.0 PHY module = 1;else = 0*/
  262. clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_24,
  263. PDRSTN_SPLIT_MASK,
  264. (0 << PDRSTN_SPLIT_SHIFT) & PDRSTN_SPLIT_MASK);
  265. }
  266. SYS_IOMUX_DOEN(25, LOW);
  267. SYS_IOMUX_DOUT(25, 7);
  268. }
  269. #if CONFIG_IS_ENABLED(STARFIVE_OTP)
  270. static void get_cpu_voltage_type(struct udevice *dev)
  271. {
  272. int ret;
  273. u32 buf = CPU_VOL_1040;
  274. ret = misc_read(dev, CPU_VOL_BINNING_OFFSET, &buf, sizeof(buf));
  275. if (ret != sizeof(buf))
  276. printf("%s: error reading CPU vol from OTP\n", __func__);
  277. else {
  278. switch ((buf & CPU_VOL_MASK)) {
  279. case CPU_VOL_1000:
  280. env_set("cpu_max_vol", "1000000");
  281. break;
  282. case CPU_VOL_1060:
  283. env_set("cpu_max_vol", "1060000");
  284. break;
  285. case CPU_VOL_1020:
  286. env_set("cpu_max_vol", "1020000");
  287. break;
  288. default:
  289. break;
  290. }
  291. }
  292. }
  293. #endif
  294. static void jh7110_jtag_init(void)
  295. {
  296. /*jtag*/
  297. SYS_IOMUX_DOEN(36, HIGH);
  298. SYS_IOMUX_DIN(36, 4);
  299. SYS_IOMUX_DOEN(61, HIGH);
  300. SYS_IOMUX_DIN(61, 19);
  301. SYS_IOMUX_DOEN(63, HIGH);
  302. SYS_IOMUX_DIN(63, 20);
  303. SYS_IOMUX_DOEN(60, HIGH);
  304. SYS_IOMUX_DIN(60, 29);
  305. SYS_IOMUX_DOEN(44, 8);
  306. SYS_IOMUX_DOUT(44, 22);
  307. }
  308. static void jh7110_i2c_init(int id)
  309. {
  310. switch (id) {
  311. case 5:
  312. //scl
  313. SYS_IOMUX_COMPLEX(19, 79, 0, 42);
  314. //sda
  315. SYS_IOMUX_COMPLEX(20, 80, 0, 43);
  316. break;
  317. default:
  318. break;
  319. }
  320. }
  321. static void get_boot_mode(void)
  322. {
  323. u32 value;
  324. value = in_le32(AON_IOMUX_BASE + AON_GPIO_DIN_REG);
  325. switch (value & 0x03) {
  326. case BOOT_FLASH:
  327. env_set("bootmode", "flash");
  328. env_set("devnum", "1");
  329. break;
  330. case BOOT_SD:
  331. env_set("bootmode", "sd");
  332. env_set("devnum", "1");
  333. break;
  334. case BOOT_EMMC:
  335. env_set("bootmode", "emmc");
  336. env_set("devnum", "0");
  337. break;
  338. default:
  339. env_set("bootmode", "uart");
  340. env_set("devnum", "1");
  341. break;
  342. }
  343. }
  344. static void jh7110_gpio_init(void)
  345. {
  346. /* This is for fixing don't detect wm8960 occasionally.
  347. * Set scl/sda gpio output enable
  348. * Set drive strength to 12mA
  349. * Set gpio pull up
  350. */
  351. SYS_IOMUX_COMPLEX(57, 9, 0, 1);
  352. SYS_IOMUX_SET_DS(57, 3);
  353. SYS_IOMUX_SET_PULL(57, GPIO_PULL_UP);
  354. SYS_IOMUX_COMPLEX(58, 10, 0, 1);
  355. SYS_IOMUX_SET_DS(58, 3);
  356. SYS_IOMUX_SET_PULL(58, GPIO_PULL_UP);
  357. }
  358. int board_init(void)
  359. {
  360. enable_caches();
  361. jh7110_jtag_init();
  362. jh7110_timer_init();
  363. jh7110_usb_init(true);
  364. jh7110_i2c_init(5);
  365. jh7110_gpio_init();
  366. return 0;
  367. }
  368. #ifdef CONFIG_BOARD_LATE_INIT
  369. int board_late_init(void)
  370. {
  371. struct udevice *dev;
  372. int ret, offset;
  373. u8 mac0[6], mac1[6];
  374. u64 share_ram_addr;
  375. get_boot_mode();
  376. jh7110_gmac_init(get_chip_type(), get_board_type());
  377. /*
  378. * save the memory info by environment variable in u-boot,
  379. * It will used to update the memory configuration in dts,
  380. * which passed to kernel lately.
  381. */
  382. env_set_hex("memory_addr", gd->ram_base);
  383. env_set_hex("memory_size", gd->ram_size);
  384. ret = uclass_get_device(UCLASS_VIDEO, 0, &dev);
  385. if (ret)
  386. return ret;
  387. ret = video_bmp_display(dev, (ulong)&bmp_logo_bitmap[0], BMP_ALIGN_CENTER, BMP_ALIGN_CENTER, true);
  388. if (ret)
  389. goto err;
  390. /* AMP case : write MAC to share ram */
  391. offset = fdt_path_offset(gd->fdt_blob,
  392. "/chosen/opensbi-domains/rpmsg_shmem");
  393. if (offset >= 0) {
  394. share_ram_addr =
  395. fdtdec_get_uint64(gd->fdt_blob, offset, "base", 0);
  396. if (share_ram_addr) {
  397. eth_env_get_enetaddr("eth0addr", mac0);
  398. eth_env_get_enetaddr("eth1addr", mac1);
  399. memcpy((void *)share_ram_addr, mac0, 6);
  400. memcpy((void *)(share_ram_addr + 8), mac1, 6);
  401. }
  402. }
  403. err:
  404. return 0;
  405. }
  406. #endif
  407. #ifdef CONFIG_MISC_INIT_R
  408. int misc_init_r(void)
  409. {
  410. char mac0[6] = {0x6c, 0xcf, 0x39, 0x6c, 0xde, 0xad};
  411. char mac1[6] = {0x6c, 0xcf, 0x39, 0x7c, 0xae, 0x5d};
  412. #if CONFIG_IS_ENABLED(STARFIVE_OTP)
  413. struct udevice *dev;
  414. char buf[16];
  415. int ret;
  416. #define MACADDR_OFFSET 0x8
  417. ret = uclass_get_device_by_driver(UCLASS_MISC,
  418. DM_DRIVER_GET(starfive_otp), &dev);
  419. if (ret) {
  420. debug("%s: could not find otp device\n", __func__);
  421. goto err;
  422. }
  423. ret = misc_read(dev, MACADDR_OFFSET, buf, sizeof(buf));
  424. if (ret != sizeof(buf))
  425. printf("%s: error reading mac from OTP\n", __func__);
  426. else
  427. if (buf[0] != 0xff) {
  428. memcpy(mac0, buf, 6);
  429. memcpy(mac1, &buf[8], 6);
  430. }
  431. err:
  432. #endif
  433. eth_env_set_enetaddr("eth0addr", mac0);
  434. eth_env_set_enetaddr("eth1addr", mac1);
  435. get_chip_type();
  436. set_uboot_fdt_addr_env();
  437. /* Set the default cpu max voltage. */
  438. env_set("cpu_max_vol", "1040000");
  439. #if CONFIG_IS_ENABLED(STARFIVE_OTP)
  440. get_cpu_voltage_type(dev);
  441. #endif
  442. return 0;
  443. }
  444. #endif
  445. #ifdef CONFIG_ID_EEPROM
  446. #include <asm/arch/eeprom.h>
  447. #define STARFIVE_JH7110_EEPROM_DDRINFO_OFFSET 91
  448. static bool check_eeprom_dram_info(ulong size)
  449. {
  450. switch (size) {
  451. case 1:
  452. case 2:
  453. case 4:
  454. case 8:
  455. case 16:
  456. return true;
  457. default:
  458. return false;
  459. }
  460. }
  461. static int resize_ddr_from_eeprom(void)
  462. {
  463. struct udevice *dev;
  464. ulong size;
  465. u32 len = 1;
  466. u8 data = 0;
  467. int ret;
  468. /* I2C init */
  469. ret = uclass_get_device(UCLASS_I2C, 0, &dev);
  470. if (ret) {
  471. debug("I2C init failed: %d\n", ret);
  472. return 0;
  473. }
  474. /* read memory size info */
  475. ret = get_data_from_eeprom(STARFIVE_JH7110_EEPROM_DDRINFO_OFFSET, len, &data);
  476. if (ret == len) {
  477. size = hextoul(&data, NULL);
  478. if (check_eeprom_dram_info(size))
  479. return size;
  480. }
  481. return 0;
  482. }
  483. #else
  484. static int resize_ddr_from_eeprom(void)
  485. {
  486. return 0;
  487. }
  488. #endif /* CONFIG_ID_EEPROM */
  489. int board_ddr_size(void)
  490. {
  491. return resize_ddr_from_eeprom();
  492. }