stm32mp1.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
  4. */
  5. #define LOG_CATEGORY LOGC_BOARD
  6. #include <common.h>
  7. #include <adc.h>
  8. #include <bootm.h>
  9. #include <clk.h>
  10. #include <config.h>
  11. #include <dm.h>
  12. #include <env.h>
  13. #include <env_internal.h>
  14. #include <fdt_support.h>
  15. #include <g_dnl.h>
  16. #include <generic-phy.h>
  17. #include <hang.h>
  18. #include <i2c.h>
  19. #include <init.h>
  20. #include <led.h>
  21. #include <log.h>
  22. #include <malloc.h>
  23. #include <misc.h>
  24. #include <mtd_node.h>
  25. #include <net.h>
  26. #include <netdev.h>
  27. #include <phy.h>
  28. #include <remoteproc.h>
  29. #include <reset.h>
  30. #include <syscon.h>
  31. #include <usb.h>
  32. #include <watchdog.h>
  33. #include <asm/global_data.h>
  34. #include <asm/io.h>
  35. #include <asm/gpio.h>
  36. #include <asm/arch/stm32.h>
  37. #include <asm/arch/sys_proto.h>
  38. #include <jffs2/load_kernel.h>
  39. #include <linux/bitops.h>
  40. #include <linux/delay.h>
  41. #include <linux/err.h>
  42. #include <linux/iopoll.h>
  43. #include <power/regulator.h>
  44. #include <usb/dwc2_udc.h>
  45. #include "../../st/common/stusb160x.h"
  46. /* SYSCFG registers */
  47. #define SYSCFG_BOOTR 0x00
  48. #define SYSCFG_PMCSETR 0x04
  49. #define SYSCFG_IOCTRLSETR 0x18
  50. #define SYSCFG_ICNR 0x1C
  51. #define SYSCFG_CMPCR 0x20
  52. #define SYSCFG_CMPENSETR 0x24
  53. #define SYSCFG_PMCCLRR 0x44
  54. #define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0)
  55. #define SYSCFG_BOOTR_BOOTPD_SHIFT 4
  56. #define SYSCFG_IOCTRLSETR_HSLVEN_TRACE BIT(0)
  57. #define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI BIT(1)
  58. #define SYSCFG_IOCTRLSETR_HSLVEN_ETH BIT(2)
  59. #define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC BIT(3)
  60. #define SYSCFG_IOCTRLSETR_HSLVEN_SPI BIT(4)
  61. #define SYSCFG_CMPCR_SW_CTRL BIT(1)
  62. #define SYSCFG_CMPCR_READY BIT(8)
  63. #define SYSCFG_CMPENSETR_MPU_EN BIT(0)
  64. #define SYSCFG_PMCSETR_ETH_CLK_SEL BIT(16)
  65. #define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17)
  66. #define SYSCFG_PMCSETR_ETH_SELMII BIT(20)
  67. #define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21)
  68. #define SYSCFG_PMCSETR_ETH_SEL_GMII_MII 0
  69. #define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21)
  70. #define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23)
  71. /*
  72. * Get a global data pointer
  73. */
  74. DECLARE_GLOBAL_DATA_PTR;
  75. #define USB_LOW_THRESHOLD_UV 200000
  76. #define USB_WARNING_LOW_THRESHOLD_UV 660000
  77. #define USB_START_LOW_THRESHOLD_UV 1230000
  78. #define USB_START_HIGH_THRESHOLD_UV 2150000
  79. int board_early_init_f(void)
  80. {
  81. /* nothing to do, only used in SPL */
  82. return 0;
  83. }
  84. int checkboard(void)
  85. {
  86. int ret;
  87. char *mode;
  88. u32 otp;
  89. struct udevice *dev;
  90. const char *fdt_compat;
  91. int fdt_compat_len;
  92. if (IS_ENABLED(CONFIG_TFABOOT)) {
  93. if (IS_ENABLED(CONFIG_STM32MP15x_STM32IMAGE))
  94. mode = "trusted - stm32image";
  95. else
  96. mode = "trusted";
  97. } else {
  98. mode = "basic";
  99. }
  100. fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
  101. &fdt_compat_len);
  102. log_info("Board: stm32mp1 in %s mode (%s)\n", mode,
  103. fdt_compat && fdt_compat_len ? fdt_compat : "");
  104. /* display the STMicroelectronics board identification */
  105. if (CONFIG_IS_ENABLED(CMD_STBOARD)) {
  106. ret = uclass_get_device_by_driver(UCLASS_MISC,
  107. DM_DRIVER_GET(stm32mp_bsec),
  108. &dev);
  109. if (!ret)
  110. ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_BOARD),
  111. &otp, sizeof(otp));
  112. if (ret > 0 && otp)
  113. log_info("Board: MB%04x Var%d.%d Rev.%c-%02d\n",
  114. otp >> 16,
  115. (otp >> 12) & 0xF,
  116. (otp >> 4) & 0xF,
  117. ((otp >> 8) & 0xF) - 1 + 'A',
  118. otp & 0xF);
  119. }
  120. return 0;
  121. }
  122. static void board_key_check(void)
  123. {
  124. ofnode node;
  125. struct gpio_desc gpio;
  126. enum forced_boot_mode boot_mode = BOOT_NORMAL;
  127. if (!IS_ENABLED(CONFIG_FASTBOOT) && !IS_ENABLED(CONFIG_CMD_STM32PROG))
  128. return;
  129. node = ofnode_path("/config");
  130. if (!ofnode_valid(node)) {
  131. log_debug("no /config node?\n");
  132. return;
  133. }
  134. if (IS_ENABLED(CONFIG_FASTBOOT)) {
  135. if (gpio_request_by_name_nodev(node, "st,fastboot-gpios", 0,
  136. &gpio, GPIOD_IS_IN)) {
  137. log_debug("could not find a /config/st,fastboot-gpios\n");
  138. } else {
  139. udelay(20);
  140. if (dm_gpio_get_value(&gpio)) {
  141. log_notice("Fastboot key pressed, ");
  142. boot_mode = BOOT_FASTBOOT;
  143. }
  144. dm_gpio_free(NULL, &gpio);
  145. }
  146. }
  147. if (IS_ENABLED(CONFIG_CMD_STM32PROG)) {
  148. if (gpio_request_by_name_nodev(node, "st,stm32prog-gpios", 0,
  149. &gpio, GPIOD_IS_IN)) {
  150. log_debug("could not find a /config/st,stm32prog-gpios\n");
  151. } else {
  152. udelay(20);
  153. if (dm_gpio_get_value(&gpio)) {
  154. log_notice("STM32Programmer key pressed, ");
  155. boot_mode = BOOT_STM32PROG;
  156. }
  157. dm_gpio_free(NULL, &gpio);
  158. }
  159. }
  160. if (boot_mode != BOOT_NORMAL) {
  161. log_notice("entering download mode...\n");
  162. clrsetbits_le32(TAMP_BOOT_CONTEXT,
  163. TAMP_BOOT_FORCED_MASK,
  164. boot_mode);
  165. }
  166. }
  167. int g_dnl_board_usb_cable_connected(void)
  168. {
  169. struct udevice *dwc2_udc_otg;
  170. int ret;
  171. if (!IS_ENABLED(CONFIG_USB_GADGET_DWC2_OTG))
  172. return -ENODEV;
  173. /* if typec stusb160x is present, means DK1 or DK2 board */
  174. ret = stusb160x_cable_connected();
  175. if (ret >= 0)
  176. return ret;
  177. ret = uclass_get_device_by_driver(UCLASS_USB_GADGET_GENERIC,
  178. DM_DRIVER_GET(dwc2_udc_otg),
  179. &dwc2_udc_otg);
  180. if (ret) {
  181. log_debug("dwc2_udc_otg init failed\n");
  182. return ret;
  183. }
  184. return dwc2_udc_B_session_valid(dwc2_udc_otg);
  185. }
  186. #ifdef CONFIG_USB_GADGET_DOWNLOAD
  187. #define STM32MP1_G_DNL_DFU_PRODUCT_NUM 0xdf11
  188. #define STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM 0x0afb
  189. int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
  190. {
  191. if (IS_ENABLED(CONFIG_DFU_OVER_USB) &&
  192. !strcmp(name, "usb_dnl_dfu"))
  193. put_unaligned(STM32MP1_G_DNL_DFU_PRODUCT_NUM, &dev->idProduct);
  194. else if (IS_ENABLED(CONFIG_FASTBOOT) &&
  195. !strcmp(name, "usb_dnl_fastboot"))
  196. put_unaligned(STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM,
  197. &dev->idProduct);
  198. else
  199. put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM, &dev->idProduct);
  200. return 0;
  201. }
  202. #endif /* CONFIG_USB_GADGET_DOWNLOAD */
  203. static int get_led(struct udevice **dev, char *led_string)
  204. {
  205. char *led_name;
  206. int ret;
  207. led_name = fdtdec_get_config_string(gd->fdt_blob, led_string);
  208. if (!led_name) {
  209. log_debug("could not find %s config string\n", led_string);
  210. return -ENOENT;
  211. }
  212. ret = led_get_by_label(led_name, dev);
  213. if (ret) {
  214. log_debug("get=%d\n", ret);
  215. return ret;
  216. }
  217. return 0;
  218. }
  219. static int setup_led(enum led_state_t cmd)
  220. {
  221. struct udevice *dev;
  222. int ret;
  223. if (!CONFIG_IS_ENABLED(LED))
  224. return 0;
  225. ret = get_led(&dev, "u-boot,boot-led");
  226. if (ret)
  227. return ret;
  228. ret = led_set_state(dev, cmd);
  229. return ret;
  230. }
  231. static void __maybe_unused led_error_blink(u32 nb_blink)
  232. {
  233. int ret;
  234. struct udevice *led;
  235. u32 i;
  236. if (!nb_blink)
  237. return;
  238. if (CONFIG_IS_ENABLED(LED)) {
  239. ret = get_led(&led, "u-boot,error-led");
  240. if (!ret) {
  241. /* make u-boot,error-led blinking */
  242. /* if U32_MAX and 125ms interval, for 17.02 years */
  243. for (i = 0; i < 2 * nb_blink; i++) {
  244. led_set_state(led, LEDST_TOGGLE);
  245. mdelay(125);
  246. WATCHDOG_RESET();
  247. }
  248. led_set_state(led, LEDST_ON);
  249. }
  250. }
  251. /* infinite: the boot process must be stopped */
  252. if (nb_blink == U32_MAX)
  253. hang();
  254. }
  255. static int adc_measurement(ofnode node, int adc_count, int *min_uV, int *max_uV)
  256. {
  257. struct ofnode_phandle_args adc_args;
  258. struct udevice *adc;
  259. unsigned int raw;
  260. int ret, uV;
  261. int i;
  262. for (i = 0; i < adc_count; i++) {
  263. if (ofnode_parse_phandle_with_args(node, "st,adc_usb_pd",
  264. "#io-channel-cells", 0, i,
  265. &adc_args)) {
  266. log_debug("can't find /config/st,adc_usb_pd\n");
  267. return 0;
  268. }
  269. ret = uclass_get_device_by_ofnode(UCLASS_ADC, adc_args.node,
  270. &adc);
  271. if (ret) {
  272. log_err("Can't get adc device(%d)\n", ret);
  273. return ret;
  274. }
  275. ret = adc_channel_single_shot(adc->name, adc_args.args[0],
  276. &raw);
  277. if (ret) {
  278. log_err("single shot failed for %s[%d]!\n",
  279. adc->name, adc_args.args[0]);
  280. return ret;
  281. }
  282. /* Convert to uV */
  283. if (!adc_raw_to_uV(adc, raw, &uV)) {
  284. if (uV > *max_uV)
  285. *max_uV = uV;
  286. if (uV < *min_uV)
  287. *min_uV = uV;
  288. log_debug("%s[%02d] = %u, %d uV\n",
  289. adc->name, adc_args.args[0], raw, uV);
  290. } else {
  291. log_err("Can't get uV value for %s[%d]\n",
  292. adc->name, adc_args.args[0]);
  293. }
  294. }
  295. return 0;
  296. }
  297. static int board_check_usb_power(void)
  298. {
  299. ofnode node;
  300. int max_uV = 0;
  301. int min_uV = USB_START_HIGH_THRESHOLD_UV;
  302. int adc_count, ret;
  303. u32 nb_blink;
  304. u8 i;
  305. if (!IS_ENABLED(CONFIG_ADC))
  306. return -ENODEV;
  307. node = ofnode_path("/config");
  308. if (!ofnode_valid(node)) {
  309. log_debug("no /config node?\n");
  310. return -ENOENT;
  311. }
  312. /*
  313. * Retrieve the ADC channels devices and get measurement
  314. * for each of them
  315. */
  316. adc_count = ofnode_count_phandle_with_args(node, "st,adc_usb_pd",
  317. "#io-channel-cells", 0);
  318. if (adc_count < 0) {
  319. if (adc_count == -ENOENT)
  320. return 0;
  321. log_err("Can't find adc channel (%d)\n", adc_count);
  322. return adc_count;
  323. }
  324. /* perform maximum of 2 ADC measurements to detect power supply current */
  325. for (i = 0; i < 2; i++) {
  326. ret = adc_measurement(node, adc_count, &min_uV, &max_uV);
  327. if (ret)
  328. return ret;
  329. /*
  330. * If highest value is inside 1.23 Volts and 2.10 Volts, that means
  331. * board is plugged on an USB-C 3A power supply and boot process can
  332. * continue.
  333. */
  334. if (max_uV > USB_START_LOW_THRESHOLD_UV &&
  335. max_uV <= USB_START_HIGH_THRESHOLD_UV &&
  336. min_uV <= USB_LOW_THRESHOLD_UV)
  337. return 0;
  338. if (i == 0) {
  339. log_err("Previous ADC measurements was not the one expected, retry in 20ms\n");
  340. mdelay(20); /* equal to max tPDDebounce duration (min 10ms - max 20ms) */
  341. }
  342. }
  343. log_notice("****************************************************\n");
  344. /*
  345. * If highest and lowest value are either both below
  346. * USB_LOW_THRESHOLD_UV or both above USB_LOW_THRESHOLD_UV, that
  347. * means USB TYPE-C is in unattached mode, this is an issue, make
  348. * u-boot,error-led blinking and stop boot process.
  349. */
  350. if ((max_uV > USB_LOW_THRESHOLD_UV &&
  351. min_uV > USB_LOW_THRESHOLD_UV) ||
  352. (max_uV <= USB_LOW_THRESHOLD_UV &&
  353. min_uV <= USB_LOW_THRESHOLD_UV)) {
  354. log_notice("* ERROR USB TYPE-C connection in unattached mode *\n");
  355. log_notice("* Check that USB TYPE-C cable is correctly plugged *\n");
  356. /* with 125ms interval, led will blink for 17.02 years ....*/
  357. nb_blink = U32_MAX;
  358. }
  359. if (max_uV > USB_LOW_THRESHOLD_UV &&
  360. max_uV <= USB_WARNING_LOW_THRESHOLD_UV &&
  361. min_uV <= USB_LOW_THRESHOLD_UV) {
  362. log_notice("* WARNING 500mA power supply detected *\n");
  363. nb_blink = 2;
  364. }
  365. if (max_uV > USB_WARNING_LOW_THRESHOLD_UV &&
  366. max_uV <= USB_START_LOW_THRESHOLD_UV &&
  367. min_uV <= USB_LOW_THRESHOLD_UV) {
  368. log_notice("* WARNING 1.5A power supply detected *\n");
  369. nb_blink = 3;
  370. }
  371. /*
  372. * If highest value is above 2.15 Volts that means that the USB TypeC
  373. * supplies more than 3 Amp, this is not compliant with TypeC specification
  374. */
  375. if (max_uV > USB_START_HIGH_THRESHOLD_UV) {
  376. log_notice("* USB TYPE-C charger not compliant with *\n");
  377. log_notice("* specification *\n");
  378. log_notice("****************************************************\n\n");
  379. /* with 125ms interval, led will blink for 17.02 years ....*/
  380. nb_blink = U32_MAX;
  381. } else {
  382. log_notice("* Current too low, use a 3A power supply! *\n");
  383. log_notice("****************************************************\n\n");
  384. }
  385. led_error_blink(nb_blink);
  386. return 0;
  387. }
  388. static void sysconf_init(void)
  389. {
  390. u8 *syscfg;
  391. struct udevice *pwr_dev;
  392. struct udevice *pwr_reg;
  393. struct udevice *dev;
  394. u32 otp = 0;
  395. int ret;
  396. u32 bootr, val;
  397. syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
  398. /* interconnect update : select master using the port 1 */
  399. /* LTDC = AXI_M9 */
  400. /* GPU = AXI_M8 */
  401. /* today information is hardcoded in U-Boot */
  402. writel(BIT(9), syscfg + SYSCFG_ICNR);
  403. /* disable Pull-Down for boot pin connected to VDD */
  404. bootr = readl(syscfg + SYSCFG_BOOTR);
  405. bootr &= ~(SYSCFG_BOOTR_BOOT_MASK << SYSCFG_BOOTR_BOOTPD_SHIFT);
  406. bootr |= (bootr & SYSCFG_BOOTR_BOOT_MASK) << SYSCFG_BOOTR_BOOTPD_SHIFT;
  407. writel(bootr, syscfg + SYSCFG_BOOTR);
  408. /* High Speed Low Voltage Pad mode Enable for SPI, SDMMC, ETH, QSPI
  409. * and TRACE. Needed above ~50MHz and conditioned by AFMUX selection.
  410. * The customer will have to disable this for low frequencies
  411. * or if AFMUX is selected but the function not used, typically for
  412. * TRACE. Otherwise, impact on power consumption.
  413. *
  414. * WARNING:
  415. * enabling High Speed mode while VDD>2.7V
  416. * with the OTP product_below_2v5 (OTP 18, BIT 13)
  417. * erroneously set to 1 can damage the IC!
  418. * => U-Boot set the register only if VDD < 2.7V (in DT)
  419. * but this value need to be consistent with board design
  420. */
  421. ret = uclass_get_device_by_driver(UCLASS_PMIC,
  422. DM_DRIVER_GET(stm32mp_pwr_pmic),
  423. &pwr_dev);
  424. if (!ret && IS_ENABLED(CONFIG_DM_REGULATOR)) {
  425. ret = uclass_get_device_by_driver(UCLASS_MISC,
  426. DM_DRIVER_GET(stm32mp_bsec),
  427. &dev);
  428. if (ret) {
  429. log_err("Can't find stm32mp_bsec driver\n");
  430. return;
  431. }
  432. ret = misc_read(dev, STM32_BSEC_SHADOW(18), &otp, 4);
  433. if (ret > 0)
  434. otp = otp & BIT(13);
  435. /* get VDD = vdd-supply */
  436. ret = device_get_supply_regulator(pwr_dev, "vdd-supply",
  437. &pwr_reg);
  438. /* check if VDD is Low Voltage */
  439. if (!ret) {
  440. if (regulator_get_value(pwr_reg) < 2700000) {
  441. writel(SYSCFG_IOCTRLSETR_HSLVEN_TRACE |
  442. SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI |
  443. SYSCFG_IOCTRLSETR_HSLVEN_ETH |
  444. SYSCFG_IOCTRLSETR_HSLVEN_SDMMC |
  445. SYSCFG_IOCTRLSETR_HSLVEN_SPI,
  446. syscfg + SYSCFG_IOCTRLSETR);
  447. if (!otp)
  448. log_err("product_below_2v5=0: HSLVEN protected by HW\n");
  449. } else {
  450. if (otp)
  451. log_err("product_below_2v5=1: HSLVEN update is destructive, no update as VDD>2.7V\n");
  452. }
  453. } else {
  454. log_debug("VDD unknown");
  455. }
  456. }
  457. /* activate automatic I/O compensation
  458. * warning: need to ensure CSI enabled and ready in clock driver
  459. */
  460. writel(SYSCFG_CMPENSETR_MPU_EN, syscfg + SYSCFG_CMPENSETR);
  461. /* poll until ready (1s timeout) */
  462. ret = readl_poll_timeout(syscfg + SYSCFG_CMPCR, val,
  463. val & SYSCFG_CMPCR_READY,
  464. 1000000);
  465. if (ret) {
  466. log_err("SYSCFG: I/O compensation failed, timeout.\n");
  467. led_error_blink(10);
  468. }
  469. clrbits_le32(syscfg + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
  470. }
  471. /* Fix to make I2C1 usable on DK2 for touchscreen usage in kernel */
  472. static int dk2_i2c1_fix(void)
  473. {
  474. ofnode node;
  475. struct gpio_desc hdmi, audio;
  476. int ret = 0;
  477. if (!IS_ENABLED(CONFIG_DM_REGULATOR))
  478. return -ENODEV;
  479. node = ofnode_path("/soc/i2c@40012000/hdmi-transmitter@39");
  480. if (!ofnode_valid(node)) {
  481. log_debug("no hdmi-transmitter@39 ?\n");
  482. return -ENOENT;
  483. }
  484. if (gpio_request_by_name_nodev(node, "reset-gpios", 0,
  485. &hdmi, GPIOD_IS_OUT)) {
  486. log_debug("could not find reset-gpios\n");
  487. return -ENOENT;
  488. }
  489. node = ofnode_path("/soc/i2c@40012000/cs42l51@4a");
  490. if (!ofnode_valid(node)) {
  491. log_debug("no cs42l51@4a ?\n");
  492. return -ENOENT;
  493. }
  494. if (gpio_request_by_name_nodev(node, "reset-gpios", 0,
  495. &audio, GPIOD_IS_OUT)) {
  496. log_debug("could not find reset-gpios\n");
  497. return -ENOENT;
  498. }
  499. /* before power up, insure that HDMI and AUDIO IC is under reset */
  500. ret = dm_gpio_set_value(&hdmi, 1);
  501. if (ret) {
  502. log_err("can't set_value for hdmi_nrst gpio");
  503. goto error;
  504. }
  505. ret = dm_gpio_set_value(&audio, 1);
  506. if (ret) {
  507. log_err("can't set_value for audio_nrst gpio");
  508. goto error;
  509. }
  510. /* power-up audio IC */
  511. regulator_autoset_by_name("v1v8_audio", NULL);
  512. /* power-up HDMI IC */
  513. regulator_autoset_by_name("v1v2_hdmi", NULL);
  514. regulator_autoset_by_name("v3v3_hdmi", NULL);
  515. error:
  516. return ret;
  517. }
  518. static bool board_is_dk2(void)
  519. {
  520. if (CONFIG_IS_ENABLED(TARGET_ST_STM32MP15x) &&
  521. of_machine_is_compatible("st,stm32mp157c-dk2"))
  522. return true;
  523. return false;
  524. }
  525. static bool board_is_ev1(void)
  526. {
  527. if (CONFIG_IS_ENABLED(TARGET_ST_STM32MP15x) &&
  528. (of_machine_is_compatible("st,stm32mp157a-ev1") ||
  529. of_machine_is_compatible("st,stm32mp157c-ev1") ||
  530. of_machine_is_compatible("st,stm32mp157d-ev1") ||
  531. of_machine_is_compatible("st,stm32mp157f-ev1")))
  532. return true;
  533. return false;
  534. }
  535. /* touchscreen driver: only used for pincontrol configuration */
  536. static const struct udevice_id goodix_ids[] = {
  537. { .compatible = "goodix,gt9147", },
  538. { }
  539. };
  540. U_BOOT_DRIVER(goodix) = {
  541. .name = "goodix",
  542. .id = UCLASS_NOP,
  543. .of_match = goodix_ids,
  544. };
  545. static void board_ev1_init(void)
  546. {
  547. struct udevice *dev;
  548. /* configure IRQ line on EV1 for touchscreen before LCD reset */
  549. uclass_get_device_by_driver(UCLASS_NOP, DM_DRIVER_GET(goodix), &dev);
  550. }
  551. /* board dependent setup after realloc */
  552. int board_init(void)
  553. {
  554. /* address of boot parameters */
  555. gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
  556. if (CONFIG_IS_ENABLED(DM_GPIO_HOG))
  557. gpio_hog_probe_all();
  558. board_key_check();
  559. if (board_is_ev1())
  560. board_ev1_init();
  561. if (board_is_dk2())
  562. dk2_i2c1_fix();
  563. if (IS_ENABLED(CONFIG_DM_REGULATOR))
  564. regulators_enable_boot_on(_DEBUG);
  565. if (!IS_ENABLED(CONFIG_TFABOOT))
  566. sysconf_init();
  567. if (CONFIG_IS_ENABLED(LED))
  568. led_default_state();
  569. setup_led(LEDST_ON);
  570. return 0;
  571. }
  572. int board_late_init(void)
  573. {
  574. const void *fdt_compat;
  575. int fdt_compat_len;
  576. int ret;
  577. u32 otp;
  578. struct udevice *dev;
  579. char buf[10];
  580. char dtb_name[256];
  581. int buf_len;
  582. if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {
  583. fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
  584. &fdt_compat_len);
  585. if (fdt_compat && fdt_compat_len) {
  586. if (strncmp(fdt_compat, "st,", 3) != 0) {
  587. env_set("board_name", fdt_compat);
  588. } else {
  589. env_set("board_name", fdt_compat + 3);
  590. buf_len = sizeof(dtb_name);
  591. strncpy(dtb_name, fdt_compat + 3, buf_len);
  592. buf_len -= strlen(fdt_compat + 3);
  593. strncat(dtb_name, ".dtb", buf_len);
  594. env_set("fdtfile", dtb_name);
  595. }
  596. }
  597. ret = uclass_get_device_by_driver(UCLASS_MISC,
  598. DM_DRIVER_GET(stm32mp_bsec),
  599. &dev);
  600. if (!ret)
  601. ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_BOARD),
  602. &otp, sizeof(otp));
  603. if (ret > 0 && otp) {
  604. snprintf(buf, sizeof(buf), "0x%04x", otp >> 16);
  605. env_set("board_id", buf);
  606. snprintf(buf, sizeof(buf), "0x%04x",
  607. ((otp >> 8) & 0xF) - 1 + 0xA);
  608. env_set("board_rev", buf);
  609. }
  610. }
  611. /* for DK1/DK2 boards */
  612. board_check_usb_power();
  613. return 0;
  614. }
  615. void board_quiesce_devices(void)
  616. {
  617. setup_led(LEDST_OFF);
  618. }
  619. /* eth init function : weak called in eqos driver */
  620. int board_interface_eth_init(struct udevice *dev,
  621. phy_interface_t interface_type)
  622. {
  623. u8 *syscfg;
  624. u32 value;
  625. bool eth_clk_sel_reg = false;
  626. bool eth_ref_clk_sel_reg = false;
  627. /* Gigabit Ethernet 125MHz clock selection. */
  628. eth_clk_sel_reg = dev_read_bool(dev, "st,eth-clk-sel");
  629. /* Ethernet 50Mhz RMII clock selection */
  630. eth_ref_clk_sel_reg =
  631. dev_read_bool(dev, "st,eth-ref-clk-sel");
  632. syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
  633. if (!syscfg)
  634. return -ENODEV;
  635. switch (interface_type) {
  636. case PHY_INTERFACE_MODE_MII:
  637. value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
  638. SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
  639. log_debug("PHY_INTERFACE_MODE_MII\n");
  640. break;
  641. case PHY_INTERFACE_MODE_GMII:
  642. if (eth_clk_sel_reg)
  643. value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
  644. SYSCFG_PMCSETR_ETH_CLK_SEL;
  645. else
  646. value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII;
  647. log_debug("PHY_INTERFACE_MODE_GMII\n");
  648. break;
  649. case PHY_INTERFACE_MODE_RMII:
  650. if (eth_ref_clk_sel_reg)
  651. value = SYSCFG_PMCSETR_ETH_SEL_RMII |
  652. SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
  653. else
  654. value = SYSCFG_PMCSETR_ETH_SEL_RMII;
  655. log_debug("PHY_INTERFACE_MODE_RMII\n");
  656. break;
  657. case PHY_INTERFACE_MODE_RGMII:
  658. case PHY_INTERFACE_MODE_RGMII_ID:
  659. case PHY_INTERFACE_MODE_RGMII_RXID:
  660. case PHY_INTERFACE_MODE_RGMII_TXID:
  661. if (eth_clk_sel_reg)
  662. value = SYSCFG_PMCSETR_ETH_SEL_RGMII |
  663. SYSCFG_PMCSETR_ETH_CLK_SEL;
  664. else
  665. value = SYSCFG_PMCSETR_ETH_SEL_RGMII;
  666. log_debug("PHY_INTERFACE_MODE_RGMII\n");
  667. break;
  668. default:
  669. log_debug("Do not manage %d interface\n",
  670. interface_type);
  671. /* Do not manage others interfaces */
  672. return -EINVAL;
  673. }
  674. /* clear and set ETH configuration bits */
  675. writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII |
  676. SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL,
  677. syscfg + SYSCFG_PMCCLRR);
  678. writel(value, syscfg + SYSCFG_PMCSETR);
  679. return 0;
  680. }
  681. enum env_location env_get_location(enum env_operation op, int prio)
  682. {
  683. u32 bootmode = get_bootmode();
  684. if (prio)
  685. return ENVL_UNKNOWN;
  686. switch (bootmode & TAMP_BOOT_DEVICE_MASK) {
  687. case BOOT_FLASH_SD:
  688. case BOOT_FLASH_EMMC:
  689. if (CONFIG_IS_ENABLED(ENV_IS_IN_MMC))
  690. return ENVL_MMC;
  691. else if (CONFIG_IS_ENABLED(ENV_IS_IN_EXT4))
  692. return ENVL_EXT4;
  693. else
  694. return ENVL_NOWHERE;
  695. case BOOT_FLASH_NAND:
  696. case BOOT_FLASH_SPINAND:
  697. if (CONFIG_IS_ENABLED(ENV_IS_IN_UBI))
  698. return ENVL_UBI;
  699. else
  700. return ENVL_NOWHERE;
  701. case BOOT_FLASH_NOR:
  702. if (CONFIG_IS_ENABLED(ENV_IS_IN_SPI_FLASH))
  703. return ENVL_SPI_FLASH;
  704. else
  705. return ENVL_NOWHERE;
  706. default:
  707. return ENVL_NOWHERE;
  708. }
  709. }
  710. const char *env_ext4_get_intf(void)
  711. {
  712. u32 bootmode = get_bootmode();
  713. switch (bootmode & TAMP_BOOT_DEVICE_MASK) {
  714. case BOOT_FLASH_SD:
  715. case BOOT_FLASH_EMMC:
  716. return "mmc";
  717. default:
  718. return "";
  719. }
  720. }
  721. int mmc_get_boot(void)
  722. {
  723. struct udevice *dev;
  724. u32 boot_mode = get_bootmode();
  725. unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
  726. char cmd[20];
  727. const u32 sdmmc_addr[] = {
  728. STM32_SDMMC1_BASE,
  729. STM32_SDMMC2_BASE,
  730. STM32_SDMMC3_BASE
  731. };
  732. if (instance > ARRAY_SIZE(sdmmc_addr))
  733. return 0;
  734. /* search associated sdmmc node in devicetree */
  735. snprintf(cmd, sizeof(cmd), "mmc@%x", sdmmc_addr[instance]);
  736. if (uclass_get_device_by_name(UCLASS_MMC, cmd, &dev)) {
  737. log_err("mmc%d = %s not found in device tree!\n", instance, cmd);
  738. return 0;
  739. }
  740. return dev_seq(dev);
  741. };
  742. const char *env_ext4_get_dev_part(void)
  743. {
  744. static char *const env_dev_part =
  745. #ifdef CONFIG_ENV_EXT4_DEVICE_AND_PART
  746. CONFIG_ENV_EXT4_DEVICE_AND_PART;
  747. #else
  748. "";
  749. #endif
  750. static char *const dev_part[] = {"0:auto", "1:auto", "2:auto"};
  751. if (strlen(env_dev_part) > 0)
  752. return env_dev_part;
  753. return dev_part[mmc_get_boot()];
  754. }
  755. int mmc_get_env_dev(void)
  756. {
  757. if (CONFIG_SYS_MMC_ENV_DEV >= 0)
  758. return CONFIG_SYS_MMC_ENV_DEV;
  759. /* use boot instance to select the correct mmc device identifier */
  760. return mmc_get_boot();
  761. }
  762. #if defined(CONFIG_OF_BOARD_SETUP)
  763. int ft_board_setup(void *blob, struct bd_info *bd)
  764. {
  765. static const struct node_info nodes[] = {
  766. { "st,stm32f469-qspi", MTD_DEV_TYPE_NOR, },
  767. { "st,stm32f469-qspi", MTD_DEV_TYPE_SPINAND},
  768. { "st,stm32mp15-fmc2", MTD_DEV_TYPE_NAND, },
  769. { "st,stm32mp1-fmc2-nfc", MTD_DEV_TYPE_NAND, },
  770. };
  771. char *boot_device;
  772. /* Check the boot-source and don't update MTD for serial or usb boot */
  773. boot_device = env_get("boot_device");
  774. if (!boot_device ||
  775. (strcmp(boot_device, "serial") && strcmp(boot_device, "usb")))
  776. if (IS_ENABLED(CONFIG_FDT_FIXUP_PARTITIONS))
  777. fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
  778. return 0;
  779. }
  780. #endif
  781. static void board_copro_image_process(ulong fw_image, size_t fw_size)
  782. {
  783. int ret, id = 0; /* Copro id fixed to 0 as only one coproc on mp1 */
  784. if (!rproc_is_initialized())
  785. if (rproc_init()) {
  786. log_err("Remote Processor %d initialization failed\n",
  787. id);
  788. return;
  789. }
  790. ret = rproc_load(id, fw_image, fw_size);
  791. log_err("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
  792. id, fw_image, fw_size, ret ? " Failed!" : " Success!");
  793. if (!ret)
  794. rproc_start(id);
  795. }
  796. U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_COPRO, board_copro_image_process);