socrates.c 5.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2008
  4. * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
  5. *
  6. * Copyright 2004 Freescale Semiconductor.
  7. * (C) Copyright 2002,2003, Motorola Inc.
  8. * Xianghua Xiao, (X.Xiao@motorola.com)
  9. *
  10. * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
  11. */
  12. #include <common.h>
  13. #include <clock_legacy.h>
  14. #include <env.h>
  15. #include <init.h>
  16. #include <pci.h>
  17. #include <uuid.h>
  18. #include <asm/global_data.h>
  19. #include <asm/processor.h>
  20. #include <asm/immap_85xx.h>
  21. #include <ioports.h>
  22. #include <flash.h>
  23. #include <linux/delay.h>
  24. #include <linux/libfdt.h>
  25. #include <fdt_support.h>
  26. #include <asm/io.h>
  27. #include <i2c.h>
  28. #include <video_fb.h>
  29. #include "upm_table.h"
  30. DECLARE_GLOBAL_DATA_PTR;
  31. extern flash_info_t flash_info[]; /* FLASH chips info */
  32. void local_bus_init (void);
  33. ulong flash_get_size (ulong base, int banknum);
  34. int checkboard (void)
  35. {
  36. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  37. char buf[64];
  38. int f;
  39. int i = env_get_f("serial#", buf, sizeof(buf));
  40. #ifdef CONFIG_PCI
  41. char *src;
  42. #endif
  43. puts("Board: Socrates");
  44. if (i > 0) {
  45. puts(", serial# ");
  46. puts(buf);
  47. }
  48. putc('\n');
  49. #if defined(CONFIG_PCI)
  50. /* Check the PCI_clk sel bit */
  51. if (in_be32(&gur->porpllsr) & (1<<15)) {
  52. src = "SYSCLK";
  53. f = CONFIG_SYS_CLK_FREQ;
  54. } else {
  55. src = "PCI_CLK";
  56. f = CONFIG_PCI_CLK_FREQ;
  57. }
  58. printf ("PCI1: 32 bit, %d MHz (%s)\n", f/1000000, src);
  59. #else
  60. printf ("PCI1: disabled\n");
  61. #endif
  62. /*
  63. * Initialize local bus.
  64. */
  65. local_bus_init ();
  66. return 0;
  67. }
  68. int misc_init_r (void)
  69. {
  70. /*
  71. * Adjust flash start and offset to detected values
  72. */
  73. gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
  74. gd->bd->bi_flashoffset = 0;
  75. /*
  76. * Check if boot FLASH isn't max size
  77. */
  78. if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) {
  79. set_lbc_or(0, gd->bd->bi_flashstart |
  80. (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
  81. set_lbc_br(0, gd->bd->bi_flashstart |
  82. (CONFIG_SYS_BR0_PRELIM & 0x00007fff));
  83. /*
  84. * Re-check to get correct base address
  85. */
  86. flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1);
  87. }
  88. /*
  89. * Check if only one FLASH bank is available
  90. */
  91. if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
  92. set_lbc_or(1, 0);
  93. set_lbc_br(1, 0);
  94. /*
  95. * Re-do flash protection upon new addresses
  96. */
  97. flash_protect(FLAG_PROTECT_CLEAR,
  98. gd->bd->bi_flashstart, 0xffffffff,
  99. &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
  100. /* Monitor protection ON by default */
  101. flash_protect(FLAG_PROTECT_SET,
  102. CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE +
  103. monitor_flash_len - 1,
  104. &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
  105. /* Environment protection ON by default */
  106. flash_protect(FLAG_PROTECT_SET,
  107. CONFIG_ENV_ADDR,
  108. CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
  109. &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
  110. /* Redundant environment protection ON by default */
  111. flash_protect(FLAG_PROTECT_SET,
  112. CONFIG_ENV_ADDR_REDUND,
  113. CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
  114. &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
  115. }
  116. pci_init();
  117. return 0;
  118. }
  119. /*
  120. * Initialize Local Bus
  121. */
  122. void local_bus_init (void)
  123. {
  124. volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
  125. volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
  126. sys_info_t sysinfo;
  127. uint clkdiv;
  128. uint lbc_mhz;
  129. uint lcrr = CONFIG_SYS_LBC_LCRR;
  130. get_sys_info (&sysinfo);
  131. clkdiv = lbc->lcrr & LCRR_CLKDIV;
  132. lbc_mhz = sysinfo.freq_systembus / 1000000 / clkdiv;
  133. /* Disable PLL bypass for Local Bus Clock >= 66 MHz */
  134. if (lbc_mhz >= 66)
  135. lcrr &= ~LCRR_DBYP; /* DLL Enabled */
  136. else
  137. lcrr |= LCRR_DBYP; /* DLL Bypass */
  138. out_be32 (&lbc->lcrr, lcrr);
  139. asm ("sync;isync;msync");
  140. out_be32 (&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */
  141. out_be32 (&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */
  142. out_be32 (&ecm->eedr, 0xffffffff); /* Clear ecm errors */
  143. out_be32 (&ecm->eeer, 0xffffffff); /* Enable ecm errors */
  144. /* Init UPMA for FPGA access */
  145. out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */
  146. upmconfig(UPMA, (uint *)UPMTableA, sizeof(UPMTableA) / sizeof(int));
  147. /* Init UPMB for Lime controller access */
  148. out_be32 (&lbc->mbmr, 0x444440); /* Use a customer-supplied value */
  149. upmconfig(UPMB, (uint *)UPMTableB, sizeof(UPMTableB) / sizeof(int));
  150. }
  151. #ifdef CONFIG_BOARD_EARLY_INIT_R
  152. int board_early_init_r (void)
  153. {
  154. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  155. /* set and reset the GPIO pin 2 which will reset the W83782G chip */
  156. out_8((unsigned char*)&gur->gpoutdr, 0x3F );
  157. out_be32((unsigned int*)&gur->gpiocr, 0x200 ); /* enable GPOut */
  158. udelay(200);
  159. out_8( (unsigned char*)&gur->gpoutdr, 0x1F );
  160. return (0);
  161. }
  162. #endif /* CONFIG_BOARD_EARLY_INIT_R */
  163. #ifdef CONFIG_OF_BOARD_SETUP
  164. int ft_board_setup(void *blob, struct bd_info *bd)
  165. {
  166. u32 val[12];
  167. int rc, i = 0;
  168. ft_cpu_setup(blob, bd);
  169. /* Fixup NOR FLASH mapping */
  170. val[i++] = 0; /* chip select number */
  171. val[i++] = 0; /* always 0 */
  172. val[i++] = gd->bd->bi_flashstart;
  173. val[i++] = gd->bd->bi_flashsize;
  174. /* Fixup FPGA mapping */
  175. val[i++] = 3; /* chip select number */
  176. val[i++] = 0; /* always 0 */
  177. val[i++] = CONFIG_SYS_FPGA_BASE;
  178. val[i++] = CONFIG_SYS_FPGA_SIZE;
  179. rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
  180. val, i * sizeof(u32), 1);
  181. if (rc)
  182. printf("Unable to update localbus ranges, err=%s\n",
  183. fdt_strerror(rc));
  184. return 0;
  185. }
  186. #endif /* CONFIG_OF_BOARD_SETUP */
  187. #if defined(CONFIG_OF_SEPARATE)
  188. void *board_fdt_blob_setup(void)
  189. {
  190. void *fw_dtb;
  191. fw_dtb = (void *)(CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SECT_SIZE);
  192. if (fdt_magic(fw_dtb) != FDT_MAGIC) {
  193. printf("DTB is not passed via %x\n", (u32)fw_dtb);
  194. return NULL;
  195. }
  196. return fw_dtb;
  197. }
  198. #endif
  199. int get_serial_clock(void)
  200. {
  201. return 333333330;
  202. }