ddr.c 1.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2008 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <fsl_ddr_sdram.h>
  7. #include <fsl_ddr_dimm_params.h>
  8. void fsl_ddr_board_options(memctl_options_t *popts,
  9. dimm_params_t *pdimm,
  10. unsigned int ctrl_num)
  11. {
  12. /*
  13. * Factors to consider for clock adjust:
  14. * - number of chips on bus
  15. * - position of slot
  16. * - DDR1 vs. DDR2?
  17. * - ???
  18. *
  19. * This needs to be determined on a board-by-board basis.
  20. * 0110 3/4 cycle late
  21. * 0111 7/8 cycle late
  22. */
  23. popts->clk_adjust = 7;
  24. /*
  25. * Factors to consider for CPO:
  26. * - frequency
  27. * - ddr1 vs. ddr2
  28. */
  29. popts->cpo_override = 0;
  30. /*
  31. * Factors to consider for write data delay:
  32. * - number of DIMMs
  33. *
  34. * 1 = 1/4 clock delay
  35. * 2 = 1/2 clock delay
  36. * 3 = 3/4 clock delay
  37. * 4 = 1 clock delay
  38. * 5 = 5/4 clock delay
  39. * 6 = 3/2 clock delay
  40. */
  41. popts->write_data_delay = 3;
  42. /*
  43. * Factors to consider for half-strength driver enable:
  44. * - number of DIMMs installed
  45. */
  46. popts->half_strength_driver_enable = 0;
  47. }