spl.c 2.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2020-2021 SiFive, Inc
  4. *
  5. * Authors:
  6. * Pragnesh Patel <pragnesh.patel@sifive.com>
  7. */
  8. #include <init.h>
  9. #include <spl.h>
  10. #include <misc.h>
  11. #include <log.h>
  12. #include <linux/delay.h>
  13. #include <linux/io.h>
  14. #include <asm/gpio.h>
  15. #include <asm/arch/gpio.h>
  16. #include <asm/arch/spl.h>
  17. #define UBRDG_RESET SIFIVE_GENERIC_GPIO_NR(0, 7)
  18. #define ULPI_RESET SIFIVE_GENERIC_GPIO_NR(0, 9)
  19. #define UHUB_RESET SIFIVE_GENERIC_GPIO_NR(0, 11)
  20. #define GEM_PHY_RESET SIFIVE_GENERIC_GPIO_NR(0, 12)
  21. #define MODE_SELECT_REG 0x1000
  22. #define MODE_SELECT_SD 0xb
  23. #define MODE_SELECT_MASK GENMASK(3, 0)
  24. static inline int spl_reset_device_by_gpio(const char *label, int pin, int low_width)
  25. {
  26. int ret;
  27. ret = gpio_request(pin, label);
  28. if (ret) {
  29. debug("%s gpio request failed: %d\n", label, ret);
  30. return ret;
  31. }
  32. ret = gpio_direction_output(pin, 1);
  33. if (ret) {
  34. debug("%s gpio direction set failed: %d\n", label, ret);
  35. return ret;
  36. }
  37. udelay(1);
  38. gpio_set_value(pin, 0);
  39. udelay(low_width);
  40. gpio_set_value(pin, 1);
  41. return ret;
  42. }
  43. static inline int spl_gemgxl_init(void)
  44. {
  45. int ret;
  46. /*
  47. * GEMGXL init VSC8541 PHY reset sequence;
  48. * leave pull-down active for 2ms
  49. */
  50. udelay(2000);
  51. ret = spl_reset_device_by_gpio("gem_phy_reset", GEM_PHY_RESET, 1);
  52. mdelay(15);
  53. return ret;
  54. }
  55. static inline int spl_usb_pcie_bridge_init(void)
  56. {
  57. return spl_reset_device_by_gpio("usb_pcie_bridge_reset", UBRDG_RESET, 3000);
  58. }
  59. static inline int spl_usb_hub_init(void)
  60. {
  61. return spl_reset_device_by_gpio("usb_hub_reset", UHUB_RESET, 100);
  62. }
  63. static inline int spl_ulpi_init(void)
  64. {
  65. return spl_reset_device_by_gpio("ulpi_reset", ULPI_RESET, 1);
  66. }
  67. int spl_board_init_f(void)
  68. {
  69. int ret;
  70. ret = spl_soc_init();
  71. if (ret) {
  72. debug("HiFive Unmatched FU740 SPL init failed: %d\n", ret);
  73. goto end;
  74. }
  75. ret = spl_gemgxl_init();
  76. if (ret) {
  77. debug("Gigabit ethernet PHY (VSC8541) init failed: %d\n", ret);
  78. goto end;
  79. }
  80. ret = spl_usb_pcie_bridge_init();
  81. if (ret) {
  82. debug("USB Bridge (ASM1042A) init failed: %d\n", ret);
  83. goto end;
  84. }
  85. ret = spl_usb_hub_init();
  86. if (ret) {
  87. debug("USB Hub (ASM1074) init failed: %d\n", ret);
  88. goto end;
  89. }
  90. ret = spl_ulpi_init();
  91. if (ret) {
  92. debug("USB 2.0 PHY (USB3320C) init failed: %d\n", ret);
  93. goto end;
  94. }
  95. end:
  96. return ret;
  97. }
  98. u32 spl_boot_device(void)
  99. {
  100. u32 mode_select = readl((void *)MODE_SELECT_REG);
  101. u32 boot_device = mode_select & MODE_SELECT_MASK;
  102. switch (boot_device) {
  103. case MODE_SELECT_SD:
  104. return BOOT_DEVICE_MMC1;
  105. default:
  106. debug("Unsupported boot device 0x%x but trying MMC1\n",
  107. boot_device);
  108. return BOOT_DEVICE_MMC1;
  109. }
  110. }
  111. #ifdef CONFIG_SPL_LOAD_FIT
  112. int board_fit_config_name_match(const char *name)
  113. {
  114. /* boot using first FIT config */
  115. return 0;
  116. }
  117. #endif