setup.h 20 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Machine Specific Values for TRATS board based on EXYNOS4210
  4. *
  5. * Copyright (C) 2011 Samsung Electronics
  6. * Heungjun Kim <riverful.kim@samsung.com>
  7. */
  8. #ifndef _TRATS_SETUP_H
  9. #define _TRATS_SETUP_H
  10. #include <config.h>
  11. #include <asm/arch/cpu.h>
  12. /* CLK_SRC_CPU: APLL(1), MPLL(1), CORE(0), HPM(0) */
  13. #define MUX_HPM_SEL_MOUTAPLL 0x0
  14. #define MUX_HPM_SEL_SCLKMPLL 0x1
  15. #define MUX_CORE_SEL_MOUTAPLL 0x0
  16. #define MUX_CORE_SEL_SCLKMPLL 0x1
  17. #define MUX_MPLL_SEL_FILPLL 0x0
  18. #define MUX_MPLL_SEL_MOUTMPLLFOUT 0x1
  19. #define MUX_APLL_SEL_FILPLL 0x0
  20. #define MUX_APLL_SEL_MOUTMPLLFOUT 0x1
  21. #define CLK_SRC_CPU_VAL ((MUX_HPM_SEL_MOUTAPLL << 20) \
  22. | (MUX_CORE_SEL_MOUTAPLL << 16) \
  23. | (MUX_MPLL_SEL_MOUTMPLLFOUT << 8)\
  24. | (MUX_APLL_SEL_MOUTMPLLFOUT << 0))
  25. /* CLK_DIV_CPU0 */
  26. #define APLL_RATIO 0x0
  27. #define PCLK_DBG_RATIO 0x1
  28. #define ATB_RATIO 0x3
  29. #define PERIPH_RATIO 0x3
  30. #define COREM1_RATIO 0x7
  31. #define COREM0_RATIO 0x3
  32. #define CORE_RATIO 0x0
  33. #define CLK_DIV_CPU0_VAL ((APLL_RATIO << 24) \
  34. | (PCLK_DBG_RATIO << 20) \
  35. | (ATB_RATIO << 16) \
  36. | (PERIPH_RATIO << 12) \
  37. | (COREM1_RATIO << 8) \
  38. | (COREM0_RATIO << 4) \
  39. | (CORE_RATIO << 0))
  40. /* CLK_DIV_CPU1 */
  41. #define HPM_RATIO 0x0
  42. #define COPY_RATIO 0x3
  43. #define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) | (COPY_RATIO))
  44. /* CLK_DIV_DMC0 */
  45. #define CORE_TIMERS_RATIO 0x1
  46. #define COPY2_RATIO 0x3
  47. #define DMCP_RATIO 0x1
  48. #define DMCD_RATIO 0x1
  49. #define DMC_RATIO 0x1
  50. #define DPHY_RATIO 0x1
  51. #define ACP_PCLK_RATIO 0x1
  52. #define ACP_RATIO 0x3
  53. #define CLK_DIV_DMC0_VAL ((CORE_TIMERS_RATIO << 28) \
  54. | (COPY2_RATIO << 24) \
  55. | (DMCP_RATIO << 20) \
  56. | (DMCD_RATIO << 16) \
  57. | (DMC_RATIO << 12) \
  58. | (DPHY_RATIO << 8) \
  59. | (ACP_PCLK_RATIO << 4) \
  60. | (ACP_RATIO << 0))
  61. /* CLK_DIV_DMC1 */
  62. #define DPM_RATIO 0x1
  63. #define DVSEM_RATIO 0x1
  64. #define PWI_RATIO 0x1
  65. #define CLK_DIV_DMC1_VAL ((DPM_RATIO << 24) \
  66. | (DVSEM_RATIO << 16) \
  67. | (PWI_RATIO << 8))
  68. /* CLK_SRC_TOP0 */
  69. #define MUX_ONENAND_SEL_ACLK_133 0x0
  70. #define MUX_ONENAND_SEL_ACLK_160 0x1
  71. #define MUX_ACLK_133_SEL_SCLKMPLL 0x0
  72. #define MUX_ACLK_133_SEL_SCLKAPLL 0x1
  73. #define MUX_ACLK_160_SEL_SCLKMPLL 0x0
  74. #define MUX_ACLK_160_SEL_SCLKAPLL 0x1
  75. #define MUX_ACLK_100_SEL_SCLKMPLL 0x0
  76. #define MUX_ACLK_100_SEL_SCLKAPLL 0x1
  77. #define MUX_ACLK_200_SEL_SCLKMPLL 0x0
  78. #define MUX_ACLK_200_SEL_SCLKAPLL 0x1
  79. #define MUX_VPLL_SEL_FINPLL 0x0
  80. #define MUX_VPLL_SEL_FOUTVPLL 0x1
  81. #define MUX_EPLL_SEL_FINPLL 0x0
  82. #define MUX_EPLL_SEL_FOUTEPLL 0x1
  83. #define MUX_ONENAND_1_SEL_MOUTONENAND 0x0
  84. #define MUX_ONENAND_1_SEL_SCLKVPLL 0x1
  85. #define CLK_SRC_TOP0_VAL ((MUX_ONENAND_SEL_ACLK_160 << 28) \
  86. | (MUX_ACLK_133_SEL_SCLKMPLL << 24) \
  87. | (MUX_ACLK_160_SEL_SCLKMPLL << 20) \
  88. | (MUX_ACLK_100_SEL_SCLKMPLL << 16) \
  89. | (MUX_ACLK_200_SEL_SCLKMPLL << 12) \
  90. | (MUX_VPLL_SEL_FOUTVPLL << 8) \
  91. | (MUX_EPLL_SEL_FOUTEPLL << 4) \
  92. | (MUX_ONENAND_1_SEL_MOUTONENAND << 0))
  93. /* CLK_DIV_TOP */
  94. #define ONENAND_RATIO 0x0
  95. #define ACLK_133_RATIO 0x5
  96. #define ACLK_160_RATIO 0x4
  97. #define ACLK_100_RATIO 0x7
  98. #define ACLK_200_RATIO 0x3
  99. #define CLK_DIV_TOP_VAL ((ONENAND_RATIO << 16) \
  100. | (ACLK_133_RATIO << 12)\
  101. | (ACLK_160_RATIO << 8) \
  102. | (ACLK_100_RATIO << 4) \
  103. | (ACLK_200_RATIO << 0))
  104. /* CLK_DIV_LEFTBUS */
  105. #define GPL_RATIO 0x1
  106. #define GDL_RATIO 0x3
  107. #define CLK_DIV_LEFTBUS_VAL ((GPL_RATIO << 4) | (GDL_RATIO))
  108. /* CLK_DIV_RIGHTBUS */
  109. #define GPR_RATIO 0x1
  110. #define GDR_RATIO 0x3
  111. #define CLK_DIV_RIGHTBUS_VAL ((GPR_RATIO << 4) | (GDR_RATIO))
  112. /* CLK_SRS_FSYS: 6 = SCLKMPLL */
  113. #define SATA_SEL_SCLKMPLL 0
  114. #define SATA_SEL_SCLKAPLL 1
  115. #define MMC_SEL_XXTI 0
  116. #define MMC_SEL_XUSBXTI 1
  117. #define MMC_SEL_SCLK_HDMI24M 2
  118. #define MMC_SEL_SCLK_USBPHY0 3
  119. #define MMC_SEL_SCLK_USBPHY1 4
  120. #define MMC_SEL_SCLK_HDMIPHY 5
  121. #define MMC_SEL_SCLKMPLL 6
  122. #define MMC_SEL_SCLKEPLL 7
  123. #define MMC_SEL_SCLKVPLL 8
  124. #define MMCC0_SEL MMC_SEL_SCLKMPLL
  125. #define MMCC1_SEL MMC_SEL_SCLKMPLL
  126. #define MMCC2_SEL MMC_SEL_SCLKMPLL
  127. #define MMCC3_SEL MMC_SEL_SCLKMPLL
  128. #define MMCC4_SEL MMC_SEL_SCLKMPLL
  129. #define CLK_SRC_FSYS_VAL ((SATA_SEL_SCLKMPLL << 24) \
  130. | (MMCC4_SEL << 16) \
  131. | (MMCC3_SEL << 12) \
  132. | (MMCC2_SEL << 8) \
  133. | (MMCC1_SEL << 4) \
  134. | (MMCC0_SEL << 0))
  135. /* SCLK_MMC[0-4] = MOUTMMC[0-4]/(MMC[0-4]_RATIO + 1)/(MMC[0-4]_PRE_RATIO +1) */
  136. /* CLK_DIV_FSYS1: 800(MPLL) / (15 + 1) */
  137. #define MMC0_RATIO 0xF
  138. #define MMC0_PRE_RATIO 0x0
  139. #define MMC1_RATIO 0xF
  140. #define MMC1_PRE_RATIO 0x0
  141. #define CLK_DIV_FSYS1_VAL ((MMC1_PRE_RATIO << 24) \
  142. | (MMC1_RATIO << 16) \
  143. | (MMC0_PRE_RATIO << 8) \
  144. | (MMC0_RATIO << 0))
  145. /* CLK_DIV_FSYS2: 800(MPLL) / (15 + 1) */
  146. #define MMC2_RATIO 0xF
  147. #define MMC2_PRE_RATIO 0x0
  148. #define MMC3_RATIO 0xF
  149. #define MMC3_PRE_RATIO 0x0
  150. #define CLK_DIV_FSYS2_VAL ((MMC3_PRE_RATIO << 24) \
  151. | (MMC3_RATIO << 16) \
  152. | (MMC2_PRE_RATIO << 8) \
  153. | (MMC2_RATIO << 0))
  154. /* CLK_DIV_FSYS3: 800(MPLL) / (15 + 1) */
  155. #define MMC4_RATIO 0xF
  156. #define MMC4_PRE_RATIO 0x0
  157. #define CLK_DIV_FSYS3_VAL ((MMC4_PRE_RATIO << 8) \
  158. | (MMC4_RATIO << 0))
  159. /* CLK_SRC_PERIL0 */
  160. #define UART_SEL_XXTI 0
  161. #define UART_SEL_XUSBXTI 1
  162. #define UART_SEL_SCLK_HDMI24M 2
  163. #define UART_SEL_SCLK_USBPHY0 3
  164. #define UART_SEL_SCLK_USBPHY1 4
  165. #define UART_SEL_SCLK_HDMIPHY 5
  166. #define UART_SEL_SCLKMPLL 6
  167. #define UART_SEL_SCLKEPLL 7
  168. #define UART_SEL_SCLKVPLL 8
  169. #define UART0_SEL UART_SEL_SCLKMPLL
  170. #define UART1_SEL UART_SEL_SCLKMPLL
  171. #define UART2_SEL UART_SEL_SCLKMPLL
  172. #define UART3_SEL UART_SEL_SCLKMPLL
  173. #define UART4_SEL UART_SEL_SCLKMPLL
  174. #define UART5_SEL UART_SEL_SCLKMPLL
  175. #define CLK_SRC_PERIL0_VAL ((UART5_SEL << 16) \
  176. | (UART4_SEL << 12) \
  177. | (UART3_SEL << 12) \
  178. | (UART2_SEL << 8) \
  179. | (UART1_SEL << 4) \
  180. | (UART0_SEL << 0))
  181. /* SCLK_UART[0-4] = MOUTUART[0-4] / (UART[0-4]_RATIO + 1) */
  182. /* CLK_DIV_PERIL0 */
  183. #define UART0_RATIO 7
  184. #define UART1_RATIO 7
  185. #define UART2_RATIO 7
  186. #define UART3_RATIO 4
  187. #define UART4_RATIO 7
  188. #define UART5_RATIO 7
  189. #define CLK_DIV_PERIL0_VAL ((UART5_RATIO << 16) \
  190. | (UART4_RATIO << 12) \
  191. | (UART3_RATIO << 12) \
  192. | (UART2_RATIO << 8) \
  193. | (UART1_RATIO << 4) \
  194. | (UART0_RATIO << 0))
  195. /* CLK_DIV_PERIL3 */
  196. #define SLIMBUS_RATIO 0x0
  197. #define PWM_RATIO 0x8
  198. #define CLK_DIV_PERIL3_VAL ((SLIMBUS_RATIO << 4) \
  199. | (PWM_RATIO << 0))
  200. /* Required period to generate a stable clock output */
  201. /* PLL_LOCK_TIME */
  202. #define PLL_LOCKTIME 0x1C20
  203. /* PLL Values */
  204. #define DISABLE 0
  205. #define ENABLE 1
  206. #define SET_PLL(mdiv, pdiv, sdiv) ((ENABLE << 31)\
  207. | (mdiv << 16) \
  208. | (pdiv << 8) \
  209. | (sdiv << 0))
  210. /* APLL_CON0: 800MHz */
  211. #define APLL_MDIV 0xC8
  212. #define APLL_PDIV 0x6
  213. #define APLL_SDIV 0x1
  214. #define APLL_CON0_VAL SET_PLL(APLL_MDIV, APLL_PDIV, APLL_SDIV)
  215. /* APLL_CON1 */
  216. #define APLL_AFC_ENB 0x1
  217. #define APLL_AFC 0x1C
  218. #define APLL_CON1_VAL ((APLL_AFC_ENB << 31) | (APLL_AFC << 0))
  219. /* MPLL_CON0: 800MHz */
  220. #define MPLL_MDIV 0xC8
  221. #define MPLL_PDIV 0x6
  222. #define MPLL_SDIV 0x1
  223. #define MPLL_CON0_VAL SET_PLL(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)
  224. /* MPLL_CON1 */
  225. #define MPLL_AFC_ENB 0x1
  226. #define MPLL_AFC 0x1C
  227. #define MPLL_CON1_VAL ((MPLL_AFC_ENB << 31) | (MPLL_AFC << 0))
  228. /* EPLL_CON0: 96MHz */
  229. #define EPLL_MDIV 0x30
  230. #define EPLL_PDIV 0x3
  231. #define EPLL_SDIV 0x2
  232. #define EPLL_CON0_VAL SET_PLL(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV)
  233. /* EPLL_CON1 */
  234. #define EPLL_K 0x0
  235. #define EPLL_CON1_VAL (EPLL_K >> 0)
  236. /* VPLL_CON0: 108MHz */
  237. #define VPLL_MDIV 0x35
  238. #define VPLL_PDIV 0x3
  239. #define VPLL_SDIV 0x2
  240. #define VPLL_CON0_VAL SET_PLL(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV)
  241. /* VPLL_CON1 */
  242. #define VPLL_SSCG_EN DISABLE
  243. #define VPLL_SEL_PF_DN_SPREAD 0x0
  244. #define VPLL_MRR 0x11
  245. #define VPLL_MFR 0x0
  246. #define VPLL_K 0x400
  247. #define VPLL_CON1_VAL ((VPLL_SSCG_EN << 31)\
  248. | (VPLL_SEL_PF_DN_SPREAD << 29) \
  249. | (VPLL_MRR << 24) \
  250. | (VPLL_MFR << 16) \
  251. | (VPLL_K << 0))
  252. /* CLOCK GATE */
  253. #define CLK_DIS 0x0
  254. #define CLK_EN 0x1
  255. #define BIT_CAM_CLK_PIXELASYNCM1 18
  256. #define BIT_CAM_CLK_PIXELASYNCM0 17
  257. #define BIT_CAM_CLK_PPMUCAMIF 16
  258. #define BIT_CAM_CLK_QEFIMC3 15
  259. #define BIT_CAM_CLK_QEFIMC2 14
  260. #define BIT_CAM_CLK_QEFIMC1 13
  261. #define BIT_CAM_CLK_QEFIMC0 12
  262. #define BIT_CAM_CLK_SMMUJPEG 11
  263. #define BIT_CAM_CLK_SMMUFIMC3 10
  264. #define BIT_CAM_CLK_SMMUFIMC2 9
  265. #define BIT_CAM_CLK_SMMUFIMC1 8
  266. #define BIT_CAM_CLK_SMMUFIMC0 7
  267. #define BIT_CAM_CLK_JPEG 6
  268. #define BIT_CAM_CLK_CSIS1 5
  269. #define BIT_CAM_CLK_CSIS0 4
  270. #define BIT_CAM_CLK_FIMC3 3
  271. #define BIT_CAM_CLK_FIMC2 2
  272. #define BIT_CAM_CLK_FIMC1 1
  273. #define BIT_CAM_CLK_FIMC0 0
  274. #define CLK_GATE_IP_CAM_ALL_EN ((CLK_EN << BIT_CAM_CLK_PIXELASYNCM1)\
  275. | (CLK_EN << BIT_CAM_CLK_PIXELASYNCM0)\
  276. | (CLK_EN << BIT_CAM_CLK_PPMUCAMIF)\
  277. | (CLK_EN << BIT_CAM_CLK_QEFIMC3)\
  278. | (CLK_EN << BIT_CAM_CLK_QEFIMC2)\
  279. | (CLK_EN << BIT_CAM_CLK_QEFIMC1)\
  280. | (CLK_EN << BIT_CAM_CLK_QEFIMC0)\
  281. | (CLK_EN << BIT_CAM_CLK_SMMUJPEG)\
  282. | (CLK_EN << BIT_CAM_CLK_SMMUFIMC3)\
  283. | (CLK_EN << BIT_CAM_CLK_SMMUFIMC2)\
  284. | (CLK_EN << BIT_CAM_CLK_SMMUFIMC1)\
  285. | (CLK_EN << BIT_CAM_CLK_SMMUFIMC0)\
  286. | (CLK_EN << BIT_CAM_CLK_JPEG)\
  287. | (CLK_EN << BIT_CAM_CLK_CSIS1)\
  288. | (CLK_EN << BIT_CAM_CLK_CSIS0)\
  289. | (CLK_EN << BIT_CAM_CLK_FIMC3)\
  290. | (CLK_EN << BIT_CAM_CLK_FIMC2)\
  291. | (CLK_EN << BIT_CAM_CLK_FIMC1)\
  292. | (CLK_EN << BIT_CAM_CLK_FIMC0))
  293. #define CLK_GATE_IP_CAM_ALL_DIS ~CLK_GATE_IP_CAM_ALL_EN
  294. #define BIT_VP_CLK_PPMUTV 5
  295. #define BIT_VP_CLK_SMMUTV 4
  296. #define BIT_VP_CLK_HDMI 3
  297. #define BIT_VP_CLK_TVENC 2
  298. #define BIT_VP_CLK_MIXER 1
  299. #define BIT_VP_CLK_VP 0
  300. #define CLK_GATE_IP_VP_ALL_EN ((CLK_EN << BIT_VP_CLK_PPMUTV)\
  301. | (CLK_EN << BIT_VP_CLK_SMMUTV)\
  302. | (CLK_EN << BIT_VP_CLK_HDMI)\
  303. | (CLK_EN << BIT_VP_CLK_TVENC)\
  304. | (CLK_EN << BIT_VP_CLK_MIXER)\
  305. | (CLK_EN << BIT_VP_CLK_VP))
  306. #define CLK_GATE_IP_VP_ALL_DIS ~CLK_GATE_IP_VP_ALL_EN
  307. #define BIT_MFC_CLK_PPMUMFC_R 4
  308. #define BIT_MFC_CLK_PPMUMFC_L 3
  309. #define BIT_MFC_CLK_SMMUMFC_R 2
  310. #define BIT_MFC_CLK_SMMUMFC_L 1
  311. #define BIT_MFC_CLK_MFC 0
  312. #define CLK_GATE_IP_MFC_ALL_EN ((CLK_EN << BIT_MFC_CLK_PPMUMFC_R)\
  313. | (CLK_EN << BIT_MFC_CLK_PPMUMFC_L)\
  314. | (CLK_EN << BIT_MFC_CLK_SMMUMFC_R)\
  315. | (CLK_EN << BIT_MFC_CLK_SMMUMFC_L)\
  316. | (CLK_EN << BIT_MFC_CLK_MFC))
  317. #define CLK_GATE_IP_MFC_ALL_DIS ~CLK_GATE_IP_MFC_ALL_EN
  318. #define BIT_G3D_CLK_QEG3D 2
  319. #define BIT_G3D_CLK_PPMUG3D 1
  320. #define BIT_G3D_CLK_G3D 0
  321. #define CLK_GATE_IP_G3D_ALL_EN ((CLK_EN << BIT_G3D_CLK_QEG3D)\
  322. | (CLK_EN << BIT_G3D_CLK_PPMUG3D)\
  323. | (CLK_EN << BIT_G3D_CLK_G3D))
  324. #define CLK_GATE_IP_G3D_ALL_DIS ~CLK_GATE_IP_G3D_ALL_EN
  325. #define BIT_IMAGE_CLK_PPMUIMAGE 9
  326. #define BIT_IMAGE_CLK_QEMDMA 8
  327. #define BIT_IMAGE_CLK_QEROTATOR 7
  328. #define BIT_IMAGE_CLK_QEG2D 6
  329. #define BIT_IMAGE_CLK_SMMUMDMA 5
  330. #define BIT_IMAGE_CLK_SMMUROTATOR 4
  331. #define BIT_IMAGE_CLK_SMMUG2D 3
  332. #define BIT_IMAGE_CLK_MDMA 2
  333. #define BIT_IMAGE_CLK_ROTATOR 1
  334. #define BIT_IMAGE_CLK_G2D 0
  335. #define CLK_GATE_IP_IMAGE_ALL_EN ((CLK_EN << BIT_IMAGE_CLK_PPMUIMAGE)\
  336. | (CLK_EN << BIT_IMAGE_CLK_QEMDMA)\
  337. | (CLK_EN << BIT_IMAGE_CLK_QEROTATOR)\
  338. | (CLK_EN << BIT_IMAGE_CLK_QEG2D)\
  339. | (CLK_EN << BIT_IMAGE_CLK_SMMUMDMA)\
  340. | (CLK_EN << BIT_IMAGE_CLK_SMMUROTATOR)\
  341. | (CLK_EN << BIT_IMAGE_CLK_SMMUG2D)\
  342. | (CLK_EN << BIT_IMAGE_CLK_MDMA)\
  343. | (CLK_EN << BIT_IMAGE_CLK_ROTATOR)\
  344. | (CLK_EN << BIT_IMAGE_CLK_G2D))
  345. #define CLK_GATE_IP_IMAGE_ALL_DIS ~CLK_GATE_IP_IMAGE_ALL_EN
  346. #define BIT_LCD0_CLK_PPMULCD0 5
  347. #define BIT_LCD0_CLK_SMMUFIMD0 4
  348. #define BIT_LCD0_CLK_DSIM0 3
  349. #define BIT_LCD0_CLK_MDNIE0 2
  350. #define BIT_LCD0_CLK_MIE0 1
  351. #define BIT_LCD0_CLK_FIMD0 0
  352. #define CLK_GATE_IP_LCD0_ALL_EN ((CLK_EN << BIT_LCD0_CLK_PPMULCD0)\
  353. | (CLK_EN << BIT_LCD0_CLK_SMMUFIMD0)\
  354. | (CLK_EN << BIT_LCD0_CLK_DSIM0)\
  355. | (CLK_EN << BIT_LCD0_CLK_MDNIE0)\
  356. | (CLK_EN << BIT_LCD0_CLK_MIE0)\
  357. | (CLK_EN << BIT_LCD0_CLK_FIMD0))
  358. #define CLK_GATE_IP_LCD0_ALL_DIS ~CLK_GATE_IP_LCD0_ALL_EN
  359. #define BIT_LCD1_CLK_PPMULCD1 5
  360. #define BIT_LCD1_CLK_SMMUFIMD1 4
  361. #define BIT_LCD1_CLK_DSIM1 3
  362. #define BIT_LCD1_CLK_MDNIE1 2
  363. #define BIT_LCD1_CLK_MIE1 1
  364. #define BIT_LCD1_CLK_FIMD1 0
  365. #define CLK_GATE_IP_LCD1_ALL_EN ((CLK_EN << BIT_LCD1_CLK_PPMULCD1)\
  366. | (CLK_EN << BIT_LCD1_CLK_SMMUFIMD1)\
  367. | (CLK_EN << BIT_LCD1_CLK_DSIM1)\
  368. | (CLK_EN << BIT_LCD1_CLK_MDNIE1)\
  369. | (CLK_EN << BIT_LCD1_CLK_MIE1)\
  370. | (CLK_EN << BIT_LCD1_CLK_FIMD1))
  371. #define CLK_GATE_IP_LCD1_ALL_DIS ~CLK_GATE_IP_LCD1_ALL_EN
  372. #define BIT_FSYS_CLK_SMMUPCIE 18
  373. #define BIT_FSYS_CLK_PPMUFILE 17
  374. #define BIT_FSYS_CLK_NFCON 16
  375. #define BIT_FSYS_CLK_ONENAND 15
  376. #define BIT_FSYS_CLK_PCIE 14
  377. #define BIT_FSYS_CLK_USBDEVICE 13
  378. #define BIT_FSYS_CLK_USBHOST 12
  379. #define BIT_FSYS_CLK_SROMC 11
  380. #define BIT_FSYS_CLK_SATA 10
  381. #define BIT_FSYS_CLK_SDMMC4 9
  382. #define BIT_FSYS_CLK_SDMMC3 8
  383. #define BIT_FSYS_CLK_SDMMC2 7
  384. #define BIT_FSYS_CLK_SDMMC1 6
  385. #define BIT_FSYS_CLK_SDMMC0 5
  386. #define BIT_FSYS_CLK_TSI 4
  387. #define BIT_FSYS_CLK_SATAPHY 3
  388. #define BIT_FSYS_CLK_PCIEPHY 2
  389. #define BIT_FSYS_CLK_PDMA1 1
  390. #define BIT_FSYS_CLK_PDMA0 0
  391. #define CLK_GATE_IP_FSYS_ALL_EN ((CLK_EN << BIT_FSYS_CLK_SMMUPCIE)\
  392. | (CLK_EN << BIT_FSYS_CLK_PPMUFILE)\
  393. | (CLK_EN << BIT_FSYS_CLK_NFCON)\
  394. | (CLK_EN << BIT_FSYS_CLK_ONENAND)\
  395. | (CLK_EN << BIT_FSYS_CLK_PCIE)\
  396. | (CLK_EN << BIT_FSYS_CLK_USBDEVICE)\
  397. | (CLK_EN << BIT_FSYS_CLK_USBHOST)\
  398. | (CLK_EN << BIT_FSYS_CLK_SROMC)\
  399. | (CLK_EN << BIT_FSYS_CLK_SATA)\
  400. | (CLK_EN << BIT_FSYS_CLK_SDMMC4)\
  401. | (CLK_EN << BIT_FSYS_CLK_SDMMC3)\
  402. | (CLK_EN << BIT_FSYS_CLK_SDMMC2)\
  403. | (CLK_EN << BIT_FSYS_CLK_SDMMC1)\
  404. | (CLK_EN << BIT_FSYS_CLK_SDMMC0)\
  405. | (CLK_EN << BIT_FSYS_CLK_TSI)\
  406. | (CLK_EN << BIT_FSYS_CLK_SATAPHY)\
  407. | (CLK_EN << BIT_FSYS_CLK_PCIEPHY)\
  408. | (CLK_EN << BIT_FSYS_CLK_PDMA1)\
  409. | (CLK_EN << BIT_FSYS_CLK_PDMA0))
  410. #define CLK_GATE_IP_FSYS_ALL_DIS ~CLK_GATE_IP_FSYS_ALL_EN
  411. #define BIT_GPS_CLK_SMMUGPS 1
  412. #define BIT_GPS_CLK_GPS 0
  413. #define CLK_GATE_IP_GPS_ALL_EN ((CLK_EN << BIT_GPS_CLK_SMMUGPS)\
  414. | (CLK_EN << BIT_GPS_CLK_GPS))
  415. #define CLK_GATE_IP_GPS_ALL_DIS ~CLK_GATE_IP_GPS_ALL_EN
  416. #define BIT_PERIL_CLK_MODEMIF 28
  417. #define BIT_PERIL_CLK_AC97 27
  418. #define BIT_PERIL_CLK_SPDIF 26
  419. #define BIT_PERIL_CLK_SLIMBUS 25
  420. #define BIT_PERIL_CLK_PWM 24
  421. #define BIT_PERIL_CLK_PCM2 23
  422. #define BIT_PERIL_CLK_PCM1 22
  423. #define BIT_PERIL_CLK_I2S2 21
  424. #define BIT_PERIL_CLK_I2S1 20
  425. #define BIT_PERIL_CLK_RESERVED0 19
  426. #define BIT_PERIL_CLK_SPI2 18
  427. #define BIT_PERIL_CLK_SPI1 17
  428. #define BIT_PERIL_CLK_SPI0 16
  429. #define BIT_PERIL_CLK_TSADC 15
  430. #define BIT_PERIL_CLK_I2CHDMI 14
  431. #define BIT_PERIL_CLK_I2C7 13
  432. #define BIT_PERIL_CLK_I2C6 12
  433. #define BIT_PERIL_CLK_I2C5 11
  434. #define BIT_PERIL_CLK_I2C4 10
  435. #define BIT_PERIL_CLK_I2C3 9
  436. #define BIT_PERIL_CLK_I2C2 8
  437. #define BIT_PERIL_CLK_I2C1 7
  438. #define BIT_PERIL_CLK_I2C0 6
  439. #define BIT_PERIL_CLK_RESERVED1 5
  440. #define BIT_PERIL_CLK_UART4 4
  441. #define BIT_PERIL_CLK_UART3 3
  442. #define BIT_PERIL_CLK_UART2 2
  443. #define BIT_PERIL_CLK_UART1 1
  444. #define BIT_PERIL_CLK_UART0 0
  445. #define CLK_GATE_IP_PERIL_ALL_EN ((CLK_EN << BIT_PERIL_CLK_MODEMIF)\
  446. | (CLK_EN << BIT_PERIL_CLK_AC97)\
  447. | (CLK_EN << BIT_PERIL_CLK_SPDIF)\
  448. | (CLK_EN << BIT_PERIL_CLK_SLIMBUS)\
  449. | (CLK_EN << BIT_PERIL_CLK_PWM)\
  450. | (CLK_EN << BIT_PERIL_CLK_PCM2)\
  451. | (CLK_EN << BIT_PERIL_CLK_PCM1)\
  452. | (CLK_EN << BIT_PERIL_CLK_I2S2)\
  453. | (CLK_EN << BIT_PERIL_CLK_I2S1)\
  454. | (CLK_EN << BIT_PERIL_CLK_RESERVED0)\
  455. | (CLK_EN << BIT_PERIL_CLK_SPI2)\
  456. | (CLK_EN << BIT_PERIL_CLK_SPI1)\
  457. | (CLK_EN << BIT_PERIL_CLK_SPI0)\
  458. | (CLK_EN << BIT_PERIL_CLK_TSADC)\
  459. | (CLK_EN << BIT_PERIL_CLK_I2CHDMI)\
  460. | (CLK_EN << BIT_PERIL_CLK_I2C7)\
  461. | (CLK_EN << BIT_PERIL_CLK_I2C6)\
  462. | (CLK_EN << BIT_PERIL_CLK_I2C5)\
  463. | (CLK_EN << BIT_PERIL_CLK_I2C4)\
  464. | (CLK_EN << BIT_PERIL_CLK_I2C3)\
  465. | (CLK_EN << BIT_PERIL_CLK_I2C2)\
  466. | (CLK_EN << BIT_PERIL_CLK_I2C1)\
  467. | (CLK_EN << BIT_PERIL_CLK_I2C0)\
  468. | (CLK_EN << BIT_PERIL_CLK_RESERVED1)\
  469. | (CLK_EN << BIT_PERIL_CLK_UART4)\
  470. | (CLK_EN << BIT_PERIL_CLK_UART3)\
  471. | (CLK_EN << BIT_PERIL_CLK_UART2)\
  472. | (CLK_EN << BIT_PERIL_CLK_UART1)\
  473. | (CLK_EN << BIT_PERIL_CLK_UART0))
  474. #define CLK_GATE_IP_PERIL_ALL_DIS ~CLK_GATE_IP_PERIL_ALL_EN
  475. #define BIT_PERIR_CLK_TMU_APBIF 17
  476. #define BIT_PERIR_CLK_KEYIF 16
  477. #define BIT_PERIR_CLK_RTC 15
  478. #define BIT_PERIR_CLK_WDT 14
  479. #define BIT_PERIR_CLK_MCT 13
  480. #define BIT_PERIR_CLK_SECKEY 12
  481. #define BIT_PERIR_CLK_HDMI_CEC 11
  482. #define BIT_PERIR_CLK_TZPC5 10
  483. #define BIT_PERIR_CLK_TZPC4 9
  484. #define BIT_PERIR_CLK_TZPC3 8
  485. #define BIT_PERIR_CLK_TZPC2 7
  486. #define BIT_PERIR_CLK_TZPC1 6
  487. #define BIT_PERIR_CLK_TZPC0 5
  488. #define BIT_PERIR_CLK_CMU_DMCPART 4
  489. #define BIT_PERIR_CLK_RESERVED 3
  490. #define BIT_PERIR_CLK_CMU_APBIF 2
  491. #define BIT_PERIR_CLK_SYSREG 1
  492. #define BIT_PERIR_CLK_CHIP_ID 0
  493. #define CLK_GATE_IP_PERIR_ALL_EN ((CLK_EN << BIT_PERIR_CLK_TMU_APBIF)\
  494. | (CLK_EN << BIT_PERIR_CLK_KEYIF)\
  495. | (CLK_EN << BIT_PERIR_CLK_RTC)\
  496. | (CLK_EN << BIT_PERIR_CLK_WDT)\
  497. | (CLK_EN << BIT_PERIR_CLK_MCT)\
  498. | (CLK_EN << BIT_PERIR_CLK_SECKEY)\
  499. | (CLK_EN << BIT_PERIR_CLK_HDMI_CEC)\
  500. | (CLK_EN << BIT_PERIR_CLK_TZPC5)\
  501. | (CLK_EN << BIT_PERIR_CLK_TZPC4)\
  502. | (CLK_EN << BIT_PERIR_CLK_TZPC3)\
  503. | (CLK_EN << BIT_PERIR_CLK_TZPC2)\
  504. | (CLK_EN << BIT_PERIR_CLK_TZPC1)\
  505. | (CLK_EN << BIT_PERIR_CLK_TZPC0)\
  506. | (CLK_EN << BIT_PERIR_CLK_CMU_DMCPART)\
  507. | (CLK_EN << BIT_PERIR_CLK_RESERVED)\
  508. | (CLK_EN << BIT_PERIR_CLK_CMU_APBIF)\
  509. | (CLK_EN << BIT_PERIR_CLK_SYSREG)\
  510. | (CLK_EN << BIT_PERIR_CLK_CHIP_ID))
  511. #define CLK_GATE_IP_PERIR_ALL_DIS ~CLK_GATE_IP_PERIR_ALL_EN
  512. #define BIT_BLOCK_CLK_GPS 7
  513. #define BIT_BLOCK_CLK_RESERVED 6
  514. #define BIT_BLOCK_CLK_LCD1 5
  515. #define BIT_BLOCK_CLK_LCD0 4
  516. #define BIT_BLOCK_CLK_G3D 3
  517. #define BIT_BLOCK_CLK_MFC 2
  518. #define BIT_BLOCK_CLK_TV 1
  519. #define BIT_BLOCK_CLK_CAM 0
  520. #define CLK_GATE_BLOCK_ALL_EN ((CLK_EN << BIT_BLOCK_CLK_GPS)\
  521. | (CLK_EN << BIT_BLOCK_CLK_RESERVED)\
  522. | (CLK_EN << BIT_BLOCK_CLK_LCD1)\
  523. | (CLK_EN << BIT_BLOCK_CLK_LCD0)\
  524. | (CLK_EN << BIT_BLOCK_CLK_G3D)\
  525. | (CLK_EN << BIT_BLOCK_CLK_MFC)\
  526. | (CLK_EN << BIT_BLOCK_CLK_TV)\
  527. | (CLK_EN << BIT_BLOCK_CLK_CAM))
  528. #define CLK_GATE_BLOCK_ALL_DIS ~CLK_GATE_BLOCK_ALL_EN
  529. /*
  530. * GATE CAM : All block
  531. * GATE VP : All block
  532. * GATE MFC : All block
  533. * GATE G3D : All block
  534. * GATE IMAGE : All block
  535. * GATE LCD0 : All block
  536. * GATE LCD1 : All block
  537. * GATE FSYS : Enable - PDMA0,1, SDMMC0,2, USBHOST, USBDEVICE, PPMUFILE
  538. * GATE GPS : All block
  539. * GATE PERI Left : All Enable, Block - SLIMBUS, SPDIF, AC97
  540. * GATE PERI Right : All Enable, Block - KEYIF
  541. * GATE Block : All block
  542. */
  543. #define CLK_GATE_IP_CAM_VAL CLK_GATE_IP_CAM_ALL_DIS
  544. #define CLK_GATE_IP_VP_VAL CLK_GATE_IP_VP_ALL_DIS
  545. #define CLK_GATE_IP_MFC_VAL CLK_GATE_IP_MFC_ALL_DIS
  546. #define CLK_GATE_IP_G3D_VAL CLK_GATE_IP_G3D_ALL_DIS
  547. #define CLK_GATE_IP_IMAGE_VAL CLK_GATE_IP_IMAGE_ALL_DIS
  548. #define CLK_GATE_IP_LCD0_VAL CLK_GATE_IP_LCD0_ALL_DIS
  549. #define CLK_GATE_IP_LCD1_VAL CLK_GATE_IP_LCD1_ALL_DIS
  550. #define CLK_GATE_IP_FSYS_VAL (CLK_GATE_IP_FSYS_ALL_DIS \
  551. | (CLK_EN << BIT_FSYS_CLK_PPMUFILE)\
  552. | (CLK_EN << BIT_FSYS_CLK_USBDEVICE)\
  553. | (CLK_EN << BIT_FSYS_CLK_USBHOST)\
  554. | (CLK_EN << BIT_FSYS_CLK_SROMC)\
  555. | (CLK_EN << BIT_FSYS_CLK_SDMMC2)\
  556. | (CLK_EN << BIT_FSYS_CLK_SDMMC0)\
  557. | (CLK_EN << BIT_FSYS_CLK_PDMA1)\
  558. | (CLK_EN << BIT_FSYS_CLK_PDMA0))
  559. #define CLK_GATE_IP_GPS_VAL CLK_GATE_IP_GPS_ALL_DIS
  560. #define CLK_GATE_IP_PERIL_VAL (CLK_GATE_IP_PERIL_ALL_DIS \
  561. | ~((CLK_EN << BIT_PERIL_CLK_AC97)\
  562. | (CLK_EN << BIT_PERIL_CLK_SPDIF)\
  563. | (CLK_EN << BIT_PERIL_CLK_I2C2)\
  564. | (CLK_EN << BIT_PERIL_CLK_SLIMBUS)))
  565. #define CLK_GATE_IP_PERIR_VAL (CLK_GATE_IP_PERIR_ALL_DIS \
  566. | ~((CLK_EN << BIT_PERIR_CLK_KEYIF)))
  567. #define CLK_GATE_BLOCK_VAL CLK_GATE_BLOCK_ALL_DIS
  568. /* PS_HOLD: Data Hight, Output En */
  569. #define BIT_DAT 8
  570. #define BIT_EN 9
  571. #define EXYNOS4_PS_HOLD_CON_VAL (0x1 << BIT_DAT | 0x1 << BIT_EN)
  572. #endif