setup.h 8.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2014 Samsung Electronics
  4. * Przemyslaw Marczak <p.marczak@samsung.com>
  5. */
  6. #ifndef __ODROIDU3_SETUP__
  7. #define __ODROIDU3_SETUP__
  8. /* A/M PLL_CON0 */
  9. #define SDIV(x) ((x) & 0x7)
  10. #define PDIV(x) (((x) & 0x3f) << 8)
  11. #define MDIV(x) (((x) & 0x3ff) << 16)
  12. #define FSEL(x) (((x) & 0x1) << 27)
  13. #define PLL_LOCKED_BIT (0x1 << 29)
  14. #define PLL_ENABLE(x) (((x) & 0x1) << 31)
  15. /* CLK_SRC_CPU */
  16. #define MUX_APLL_SEL(x) ((x) & 0x1)
  17. #define MUX_CORE_SEL(x) (((x) & 0x1) << 16)
  18. #define MUX_HPM_SEL(x) (((x) & 0x1) << 20)
  19. #define MUX_MPLL_USER_SEL_C(x) (((x) & 0x1) << 24)
  20. #define MUX_STAT_CHANGING 0x100
  21. /* CLK_MUX_STAT_CPU */
  22. #define APLL_SEL(x) ((x) & 0x7)
  23. #define CORE_SEL(x) (((x) & 0x7) << 16)
  24. #define HPM_SEL(x) (((x) & 0x7) << 20)
  25. #define MPLL_USER_SEL_C(x) (((x) & 0x7) << 24)
  26. #define MUX_STAT_CPU_CHANGING (APLL_SEL(MUX_STAT_CHANGING) | \
  27. CORE_SEL(MUX_STAT_CHANGING) | \
  28. HPM_SEL(MUX_STAT_CHANGING) | \
  29. MPLL_USER_SEL_C(MUX_STAT_CHANGING))
  30. /* CLK_DIV_CPU0 */
  31. #define CORE_RATIO(x) ((x) & 0x7)
  32. #define COREM0_RATIO(x) (((x) & 0x7) << 4)
  33. #define COREM1_RATIO(x) (((x) & 0x7) << 8)
  34. #define PERIPH_RATIO(x) (((x) & 0x7) << 12)
  35. #define ATB_RATIO(x) (((x) & 0x7) << 16)
  36. #define PCLK_DBG_RATIO(x) (((x) & 0x7) << 20)
  37. #define APLL_RATIO(x) (((x) & 0x7) << 24)
  38. #define CORE2_RATIO(x) (((x) & 0x7) << 28)
  39. /* CLK_DIV_STAT_CPU0 */
  40. #define DIV_CORE(x) ((x) & 0x1)
  41. #define DIV_COREM0(x) (((x) & 0x1) << 4)
  42. #define DIV_COREM1(x) (((x) & 0x1) << 8)
  43. #define DIV_PERIPH(x) (((x) & 0x1) << 12)
  44. #define DIV_ATB(x) (((x) & 0x1) << 16)
  45. #define DIV_PCLK_DBG(x) (((x) & 0x1) << 20)
  46. #define DIV_APLL(x) (((x) & 0x1) << 24)
  47. #define DIV_CORE2(x) (((x) & 0x1) << 28)
  48. #define DIV_STAT_CHANGING 0x1
  49. #define DIV_STAT_CPU0_CHANGING (DIV_CORE(DIV_STAT_CHANGING) | \
  50. DIV_COREM0(DIV_STAT_CHANGING) | \
  51. DIV_COREM1(DIV_STAT_CHANGING) | \
  52. DIV_PERIPH(DIV_STAT_CHANGING) | \
  53. DIV_ATB(DIV_STAT_CHANGING) | \
  54. DIV_PCLK_DBG(DIV_STAT_CHANGING) | \
  55. DIV_APLL(DIV_STAT_CHANGING) | \
  56. DIV_CORE2(DIV_STAT_CHANGING))
  57. /* CLK_DIV_CPU1 */
  58. #define COPY_RATIO(x) ((x) & 0x7)
  59. #define HPM_RATIO(x) (((x) & 0x7) << 4)
  60. #define CORES_RATIO(x) (((x) & 0x7) << 8)
  61. /* CLK_DIV_STAT_CPU1 */
  62. #define DIV_COPY(x) ((x) & 0x7)
  63. #define DIV_HPM(x) (((x) & 0x1) << 4)
  64. #define DIV_CORES(x) (((x) & 0x1) << 8)
  65. #define DIV_STAT_CPU1_CHANGING (DIV_COPY(DIV_STAT_CHANGING) | \
  66. DIV_HPM(DIV_STAT_CHANGING) | \
  67. DIV_CORES(DIV_STAT_CHANGING))
  68. /* CLK_SRC_DMC */
  69. #define MUX_C2C_SEL(x) ((x) & 0x1)
  70. #define MUX_DMC_BUS_SEL(x) (((x) & 0x1) << 4)
  71. #define MUX_DPHY_SEL(x) (((x) & 0x1) << 8)
  72. #define MUX_MPLL_SEL(x) (((x) & 0x1) << 12)
  73. #define MUX_PWI_SEL(x) (((x) & 0xf) << 16)
  74. #define MUX_G2D_ACP0_SEL(x) (((x) & 0x1) << 20)
  75. #define MUX_G2D_ACP1_SEL(x) (((x) & 0x1) << 24)
  76. #define MUX_G2D_ACP_SEL(x) (((x) & 0x1) << 28)
  77. /* CLK_MUX_STAT_DMC */
  78. #define C2C_SEL(x) (((x)) & 0x7)
  79. #define DMC_BUS_SEL(x) (((x) & 0x7) << 4)
  80. #define DPHY_SEL(x) (((x) & 0x7) << 8)
  81. #define MPLL_SEL(x) (((x) & 0x7) << 12)
  82. /* #define PWI_SEL(x) (((x) & 0xf) << 16) - Reserved */
  83. #define G2D_ACP0_SEL(x) (((x) & 0x7) << 20)
  84. #define G2D_ACP1_SEL(x) (((x) & 0x7) << 24)
  85. #define G2D_ACP_SEL(x) (((x) & 0x7) << 28)
  86. #define MUX_STAT_DMC_CHANGING (C2C_SEL(MUX_STAT_CHANGING) | \
  87. DMC_BUS_SEL(MUX_STAT_CHANGING) | \
  88. DPHY_SEL(MUX_STAT_CHANGING) | \
  89. MPLL_SEL(MUX_STAT_CHANGING) |\
  90. G2D_ACP0_SEL(MUX_STAT_CHANGING) | \
  91. G2D_ACP1_SEL(MUX_STAT_CHANGING) | \
  92. G2D_ACP_SEL(MUX_STAT_CHANGING))
  93. /* CLK_DIV_DMC0 */
  94. #define ACP_RATIO(x) ((x) & 0x7)
  95. #define ACP_PCLK_RATIO(x) (((x) & 0x7) << 4)
  96. #define DPHY_RATIO(x) (((x) & 0x7) << 8)
  97. #define DMC_RATIO(x) (((x) & 0x7) << 12)
  98. #define DMCD_RATIO(x) (((x) & 0x7) << 16)
  99. #define DMCP_RATIO(x) (((x) & 0x7) << 20)
  100. /* CLK_DIV_STAT_DMC0 */
  101. #define DIV_ACP(x) ((x) & 0x1)
  102. #define DIV_ACP_PCLK(x) (((x) & 0x1) << 4)
  103. #define DIV_DPHY(x) (((x) & 0x1) << 8)
  104. #define DIV_DMC(x) (((x) & 0x1) << 12)
  105. #define DIV_DMCD(x) (((x) & 0x1) << 16)
  106. #define DIV_DMCP(x) (((x) & 0x1) << 20)
  107. #define DIV_STAT_DMC0_CHANGING (DIV_ACP(DIV_STAT_CHANGING) | \
  108. DIV_ACP_PCLK(DIV_STAT_CHANGING) | \
  109. DIV_DPHY(DIV_STAT_CHANGING) | \
  110. DIV_DMC(DIV_STAT_CHANGING) | \
  111. DIV_DMCD(DIV_STAT_CHANGING) | \
  112. DIV_DMCP(DIV_STAT_CHANGING))
  113. /* CLK_DIV_DMC1 */
  114. #define G2D_ACP_RATIO(x) ((x) & 0xf)
  115. #define C2C_RATIO(x) (((x) & 0x7) << 4)
  116. #define PWI_RATIO(x) (((x) & 0xf) << 8)
  117. #define C2C_ACLK_RATIO(x) (((x) & 0x7) << 12)
  118. #define DVSEM_RATIO(x) (((x) & 0x7f) << 16)
  119. #define DPM_RATIO(x) (((x) & 0x7f) << 24)
  120. /* CLK_DIV_STAT_DMC1 */
  121. #define DIV_G2D_ACP(x) ((x) & 0x1)
  122. #define DIV_C2C(x) (((x) & 0x1) << 4)
  123. #define DIV_PWI(x) (((x) & 0x1) << 8)
  124. #define DIV_C2C_ACLK(x) (((x) & 0x1) << 12)
  125. #define DIV_DVSEM(x) (((x) & 0x1) << 16)
  126. #define DIV_DPM(x) (((x) & 0x1) << 24)
  127. #define DIV_STAT_DMC1_CHANGING (DIV_G2D_ACP(DIV_STAT_CHANGING) | \
  128. DIV_C2C(DIV_STAT_CHANGING) | \
  129. DIV_PWI(DIV_STAT_CHANGING) | \
  130. DIV_C2C_ACLK(DIV_STAT_CHANGING) | \
  131. DIV_DVSEM(DIV_STAT_CHANGING) | \
  132. DIV_DPM(DIV_STAT_CHANGING))
  133. /* Set CLK_SRC_PERIL0 */
  134. #define UART4_SEL(x) (((x) & 0xf) << 16)
  135. #define UART3_SEL(x) (((x) & 0xf) << 12)
  136. #define UART2_SEL(x) (((x) & 0xf) << 8)
  137. #define UART1_SEL(x) (((x) & 0xf) << 4)
  138. #define UART0_SEL(x) ((x) & 0xf)
  139. /* Set CLK_DIV_PERIL0 */
  140. #define UART4_RATIO(x) (((x) & 0xf) << 16)
  141. #define UART3_RATIO(x) (((x) & 0xf) << 12)
  142. #define UART2_RATIO(x) (((x) & 0xf) << 8)
  143. #define UART1_RATIO(x) (((x) & 0xf) << 4)
  144. #define UART0_RATIO(x) ((x) & 0xf)
  145. /* Set CLK_DIV_STAT_PERIL0 */
  146. #define DIV_UART4(x) (((x) & 0x1) << 16)
  147. #define DIV_UART3(x) (((x) & 0x1) << 12)
  148. #define DIV_UART2(x) (((x) & 0x1) << 8)
  149. #define DIV_UART1(x) (((x) & 0x1) << 4)
  150. #define DIV_UART0(x) ((x) & 0x1)
  151. #define DIV_STAT_PERIL0_CHANGING (DIV_UART4(DIV_STAT_CHANGING) | \
  152. DIV_UART3(DIV_STAT_CHANGING) | \
  153. DIV_UART2(DIV_STAT_CHANGING) | \
  154. DIV_UART1(DIV_STAT_CHANGING) | \
  155. DIV_UART0(DIV_STAT_CHANGING))
  156. /* CLK_DIV_FSYS1 */
  157. #define MMC0_RATIO(x) ((x) & 0xf)
  158. #define MMC0_PRE_RATIO(x) (((x) & 0xff) << 8)
  159. #define MMC1_RATIO(x) (((x) & 0xf) << 16)
  160. #define MMC1_PRE_RATIO(x) (((x) & 0xff) << 24)
  161. /* CLK_DIV_STAT_FSYS1 */
  162. #define DIV_MMC0(x) ((x) & 1)
  163. #define DIV_MMC0_PRE(x) (((x) & 1) << 8)
  164. #define DIV_MMC1(x) (((x) & 1) << 16)
  165. #define DIV_MMC1_PRE(x) (((x) & 1) << 24)
  166. #define DIV_STAT_FSYS1_CHANGING (DIV_MMC0(DIV_STAT_CHANGING) | \
  167. DIV_MMC0_PRE(DIV_STAT_CHANGING) | \
  168. DIV_MMC1(DIV_STAT_CHANGING) | \
  169. DIV_MMC1_PRE(DIV_STAT_CHANGING))
  170. /* CLK_DIV_FSYS2 */
  171. #define MMC2_RATIO(x) ((x) & 0xf)
  172. #define MMC2_PRE_RATIO(x) (((x) & 0xff) << 8)
  173. #define MMC3_RATIO(x) (((x) & 0xf) << 16)
  174. #define MMC3_PRE_RATIO(x) (((x) & 0xff) << 24)
  175. /* CLK_DIV_STAT_FSYS2 */
  176. #define DIV_MMC2(x) ((x) & 0x1)
  177. #define DIV_MMC2_PRE(x) (((x) & 0x1) << 8)
  178. #define DIV_MMC3(x) (((x) & 0x1) << 16)
  179. #define DIV_MMC3_PRE(x) (((x) & 0x1) << 24)
  180. #define DIV_STAT_FSYS2_CHANGING (DIV_MMC2(DIV_STAT_CHANGING) | \
  181. DIV_MMC2_PRE(DIV_STAT_CHANGING) | \
  182. DIV_MMC3(DIV_STAT_CHANGING) | \
  183. DIV_MMC3_PRE(DIV_STAT_CHANGING))
  184. /* CLK_DIV_FSYS3 */
  185. #define MMC4_RATIO(x) ((x) & 0x7)
  186. #define MMC4_PRE_RATIO(x) (((x) & 0xff) << 8)
  187. /* CLK_DIV_STAT_FSYS3 */
  188. #define DIV_MMC4(x) ((x) & 0x1)
  189. #define DIV_MMC4_PRE(x) (((x) & 0x1) << 8)
  190. #define DIV_STAT_FSYS3_CHANGING (DIV_MMC4(DIV_STAT_CHANGING) | \
  191. DIV_MMC4_PRE(DIV_STAT_CHANGING))
  192. /* XCL205 GPIO config - Odroid U3 */
  193. #define XCL205_GPIO_BASE EXYNOS4X12_GPIO_PART1_BASE
  194. #define XCL205_EN_GPIO_OFFSET 0x20 /* GPA1 */
  195. #define XCL205_EN_GPIO_PIN 1
  196. #define XCL205_EN_GPIO_CON (XCL205_GPIO_BASE + \
  197. XCL205_EN_GPIO_OFFSET)
  198. #define XCL205_EN_GPIO_CON_CFG (S5P_GPIO_OUTPUT << \
  199. 4 * XCL205_EN_GPIO_PIN)
  200. #define XCL205_EN_GPIO_DAT_CFG (0x1 << XCL205_EN_GPIO_PIN)
  201. #define XCL205_EN_GPIO_PUD_CFG (S5P_GPIO_PULL_UP << \
  202. 2 * XCL205_EN_GPIO_PIN)
  203. #define XCL205_EN_GPIO_DRV_CFG (S5P_GPIO_DRV_4X << \
  204. 2 * XCL205_EN_GPIO_PIN)
  205. #define XCL205_STATE_GPIO_OFFSET 0x80 /* GPC1 */
  206. #define XCL205_STATE_GPIO_PIN 2
  207. #define XCL205_STATE_GPIO_CON (XCL205_GPIO_BASE + \
  208. XCL205_STATE_GPIO_OFFSET)
  209. #define XCL205_STATE_GPIO_DAT XCL205_STATE_GPIO_CON + 0x4
  210. #define XCL205_STATE_GPIO_CON_CFG (S5P_GPIO_INPUT << \
  211. 4 * XCL205_STATE_GPIO_PIN)
  212. #define XCL205_STATE_GPIO_PUD_CFG (S5P_GPIO_PULL_NONE << \
  213. 2 * XCL205_STATE_GPIO_PIN)
  214. #ifdef CONFIG_BOARD_TYPES
  215. extern void sdelay(unsigned long);
  216. #endif
  217. #endif /*__ODROIDU3_SETUP__ */