rockpro64-rk3399.c 1.2 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2019 Vasily Khoruzhick <anarsoul@gmail.com>
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <init.h>
  8. #include <syscon.h>
  9. #include <asm/io.h>
  10. #include <asm/arch-rockchip/clock.h>
  11. #include <asm/arch-rockchip/grf_rk3399.h>
  12. #include <asm/arch-rockchip/hardware.h>
  13. #include <asm/arch-rockchip/misc.h>
  14. #define GRF_IO_VSEL_BT565_SHIFT 0
  15. #define PMUGRF_CON0_VSEL_SHIFT 8
  16. #ifdef CONFIG_MISC_INIT_R
  17. static void setup_iodomain(void)
  18. {
  19. struct rk3399_grf_regs *grf =
  20. syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  21. struct rk3399_pmugrf_regs *pmugrf =
  22. syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
  23. /* BT565 is in 1.8v domain */
  24. rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_BT565_SHIFT);
  25. /* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL */
  26. rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT);
  27. }
  28. int misc_init_r(void)
  29. {
  30. const u32 cpuid_offset = 0x7;
  31. const u32 cpuid_length = 0x10;
  32. u8 cpuid[cpuid_length];
  33. int ret;
  34. setup_iodomain();
  35. ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
  36. if (ret)
  37. return ret;
  38. ret = rockchip_cpuid_set(cpuid, cpuid_length);
  39. if (ret)
  40. return ret;
  41. ret = rockchip_setup_macaddr();
  42. return ret;
  43. }
  44. #endif