mux.c 4.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * mux.c
  4. *
  5. * Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH
  6. * Copyright (C) 2019 DENX Software Engineering GmbH
  7. */
  8. #include <common.h>
  9. #include <asm/arch/sys_proto.h>
  10. #include <asm/arch/hardware.h>
  11. #include <asm/arch/mux.h>
  12. #include <asm/io.h>
  13. #include "board.h"
  14. static struct module_pin_mux uart0_pin_mux[] = {
  15. {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
  16. {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
  17. {-1},
  18. };
  19. #ifdef CONFIG_MMC
  20. static struct module_pin_mux mmc0_pin_mux[] = {
  21. {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
  22. {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
  23. {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
  24. {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
  25. {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
  26. {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
  27. {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
  28. {-1},
  29. };
  30. #endif
  31. static struct module_pin_mux i2c0_pin_mux[] = {
  32. {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
  33. PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
  34. {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
  35. PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
  36. {-1},
  37. };
  38. #ifdef CONFIG_SPI
  39. static struct module_pin_mux spi0_pin_mux[] = {
  40. {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_SCLK */
  41. {OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
  42. PULLUDEN | PULLUP_EN)}, /* SPI0_D0 */
  43. {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_D1 */
  44. {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
  45. PULLUDEN | PULLUP_EN)}, /* SPI0_CS0 */
  46. {-1},
  47. };
  48. #endif
  49. static struct module_pin_mux rmii1_pin_mux[] = {
  50. {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS */
  51. {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
  52. {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
  53. {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */
  54. {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */
  55. {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
  56. {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
  57. {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
  58. {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
  59. {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */
  60. {-1},
  61. };
  62. static struct module_pin_mux cbmux_pin_mux[] = {
  63. {OFFSET(uart0_ctsn), MODE(7) | RXACTIVE | PULLDOWN_EN}, /* JP3 */
  64. {OFFSET(uart0_rtsn), MODE(7) | RXACTIVE | PULLUP_EN}, /* JP4 */
  65. {-1},
  66. };
  67. #ifdef CONFIG_MTD_RAW_NAND
  68. static struct module_pin_mux nand_pin_mux[] = {
  69. {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
  70. {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
  71. {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
  72. {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
  73. {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
  74. {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
  75. {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
  76. {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
  77. {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
  78. {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
  79. {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
  80. {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
  81. {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
  82. {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
  83. {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
  84. {-1},
  85. };
  86. #endif
  87. void enable_uart0_pin_mux(void)
  88. {
  89. configure_module_pin_mux(uart0_pin_mux);
  90. }
  91. void enable_i2c0_pin_mux(void)
  92. {
  93. configure_module_pin_mux(i2c0_pin_mux);
  94. }
  95. void enable_board_pin_mux(void)
  96. {
  97. configure_module_pin_mux(rmii1_pin_mux);
  98. configure_module_pin_mux(mmc0_pin_mux);
  99. configure_module_pin_mux(cbmux_pin_mux);
  100. #ifdef CONFIG_MTD_RAW_NAND
  101. configure_module_pin_mux(nand_pin_mux);
  102. #endif
  103. #ifdef CONFIG_SPI
  104. configure_module_pin_mux(spi0_pin_mux);
  105. #endif
  106. }