pcm052.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2018
  4. * Lukasz Majewski, DENX Software Engineering, lukma@denx.de.
  5. *
  6. * Copyright 2013 Freescale Semiconductor, Inc.
  7. */
  8. #include <common.h>
  9. #include <init.h>
  10. #include <asm/global_data.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/imx-regs.h>
  13. #include <asm/arch/iomux-vf610.h>
  14. #include <asm/arch/ddrmc-vf610.h>
  15. #include <asm/arch/crm_regs.h>
  16. #include <asm/arch/clock.h>
  17. #include <env.h>
  18. #include <led.h>
  19. #include <miiphy.h>
  20. #include <linux/bitops.h>
  21. DECLARE_GLOBAL_DATA_PTR;
  22. static struct ddrmc_cr_setting pcm052_cr_settings[] = {
  23. /* not in the datasheets, but in the original code */
  24. { 0x00002000, 105 },
  25. { 0x00000020, 110 },
  26. /* AXI */
  27. { DDRMC_CR117_AXI0_W_PRI(1) | DDRMC_CR117_AXI0_R_PRI(1), 117 },
  28. { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
  29. { DDRMC_CR120_AXI0_PRI1_RPRI(2) |
  30. DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 },
  31. { DDRMC_CR121_AXI0_PRI3_RPRI(2) |
  32. DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 },
  33. { DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
  34. DDRMC_CR122_AXI0_PRIRLX(100), 122 },
  35. { DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
  36. DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 },
  37. { DDRMC_CR124_AXI1_PRIRLX(100), 124 },
  38. { DDRMC_CR126_PHY_RDLAT(11), 126 },
  39. { DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6), 132 },
  40. { DDRMC_CR137_PHYCTL_DL(2), 137 },
  41. { DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
  42. DDRMC_CR139_PHY_WRLV_DLL(3) |
  43. DDRMC_CR139_PHY_WRLV_EN(3), 139 },
  44. { DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
  45. DDRMC_CR154_PAD_ZQ_MODE(1) |
  46. DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
  47. DDRMC_CR154_PAD_ZQ_HW_FOR(0), 154 },
  48. { DDRMC_CR155_PAD_ODT_BYTE1(5) | DDRMC_CR155_PAD_ODT_BYTE0(5), 155 },
  49. { DDRMC_CR158_TWR(6), 158 },
  50. { DDRMC_CR161_ODT_EN(0) | DDRMC_CR161_TODTH_RD(0) |
  51. DDRMC_CR161_TODTH_WR(6), 161 },
  52. /* end marker */
  53. { 0, -1 }
  54. };
  55. /* PHY settings -- most of them differ from default in imx-regs.h */
  56. #define PCM052_DDRMC_PHY_DQ_TIMING 0x00002213
  57. #define PCM052_DDRMC_PHY_CTRL 0x00290000
  58. #define PCM052_DDRMC_PHY_SLAVE_CTRL 0x00002c00
  59. #define PCM052_DDRMC_PHY_PROC_PAD_ODT 0x00010020
  60. static struct ddrmc_phy_setting pcm052_phy_settings[] = {
  61. { PCM052_DDRMC_PHY_DQ_TIMING, 0 },
  62. { PCM052_DDRMC_PHY_DQ_TIMING, 16 },
  63. { PCM052_DDRMC_PHY_DQ_TIMING, 32 },
  64. { PCM052_DDRMC_PHY_DQ_TIMING, 48 },
  65. { DDRMC_PHY_DQS_TIMING, 1 },
  66. { DDRMC_PHY_DQS_TIMING, 17 },
  67. { DDRMC_PHY_DQS_TIMING, 33 },
  68. { DDRMC_PHY_DQS_TIMING, 49 },
  69. { PCM052_DDRMC_PHY_CTRL, 2 },
  70. { PCM052_DDRMC_PHY_CTRL, 18 },
  71. { PCM052_DDRMC_PHY_CTRL, 34 },
  72. { DDRMC_PHY_MASTER_CTRL, 3 },
  73. { DDRMC_PHY_MASTER_CTRL, 19 },
  74. { DDRMC_PHY_MASTER_CTRL, 35 },
  75. { PCM052_DDRMC_PHY_SLAVE_CTRL, 4 },
  76. { PCM052_DDRMC_PHY_SLAVE_CTRL, 20 },
  77. { PCM052_DDRMC_PHY_SLAVE_CTRL, 36 },
  78. { DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, 50 },
  79. { PCM052_DDRMC_PHY_PROC_PAD_ODT, 52 },
  80. /* end marker */
  81. { 0, -1 }
  82. };
  83. int dram_init(void)
  84. {
  85. #if defined(CONFIG_TARGET_PCM052)
  86. static const struct ddr3_jedec_timings pcm052_ddr_timings = {
  87. .tinit = 5,
  88. .trst_pwron = 80000,
  89. .cke_inactive = 200000,
  90. .wrlat = 5,
  91. .caslat_lin = 12,
  92. .trc = 6,
  93. .trrd = 4,
  94. .tccd = 4,
  95. .tbst_int_interval = 4,
  96. .tfaw = 18,
  97. .trp = 6,
  98. .twtr = 4,
  99. .tras_min = 15,
  100. .tmrd = 4,
  101. .trtp = 4,
  102. .tras_max = 14040,
  103. .tmod = 12,
  104. .tckesr = 4,
  105. .tcke = 3,
  106. .trcd_int = 6,
  107. .tras_lockout = 1,
  108. .tdal = 10,
  109. .bstlen = 3,
  110. .tdll = 512,
  111. .trp_ab = 6,
  112. .tref = 1542,
  113. .trfc = 64,
  114. .tref_int = 5,
  115. .tpdex = 3,
  116. .txpdll = 10,
  117. .txsnr = 68,
  118. .txsr = 506,
  119. .cksrx = 5,
  120. .cksre = 5,
  121. .freq_chg_en = 1,
  122. .zqcl = 256,
  123. .zqinit = 512,
  124. .zqcs = 64,
  125. .ref_per_zq = 64,
  126. .zqcs_rotate = 1,
  127. .aprebit = 10,
  128. .cmd_age_cnt = 255,
  129. .age_cnt = 255,
  130. .q_fullness = 0,
  131. .odt_rd_mapcs0 = 1,
  132. .odt_wr_mapcs0 = 1,
  133. .wlmrd = 40,
  134. .wldqsen = 25,
  135. };
  136. const int row_diff = 2;
  137. #elif defined(CONFIG_TARGET_BK4R1)
  138. static const struct ddr3_jedec_timings pcm052_ddr_timings = {
  139. .tinit = 5,
  140. .trst_pwron = 80000,
  141. .cke_inactive = 200000,
  142. .wrlat = 5,
  143. .caslat_lin = 12,
  144. .trc = 6,
  145. .trrd = 4,
  146. .tccd = 4,
  147. .tbst_int_interval = 0,
  148. .tfaw = 16,
  149. .trp = 6,
  150. .twtr = 4,
  151. .tras_min = 15,
  152. .tmrd = 4,
  153. .trtp = 4,
  154. .tras_max = 28080,
  155. .tmod = 12,
  156. .tckesr = 4,
  157. .tcke = 3,
  158. .trcd_int = 6,
  159. .tras_lockout = 1,
  160. .tdal = 12,
  161. .bstlen = 3,
  162. .tdll = 512,
  163. .trp_ab = 6,
  164. .tref = 3120,
  165. .trfc = 104,
  166. .tref_int = 0,
  167. .tpdex = 3,
  168. .txpdll = 10,
  169. .txsnr = 108,
  170. .txsr = 512,
  171. .cksrx = 5,
  172. .cksre = 5,
  173. .freq_chg_en = 1,
  174. .zqcl = 256,
  175. .zqinit = 512,
  176. .zqcs = 64,
  177. .ref_per_zq = 64,
  178. .zqcs_rotate = 1,
  179. .aprebit = 10,
  180. .cmd_age_cnt = 255,
  181. .age_cnt = 255,
  182. .q_fullness = 0,
  183. .odt_rd_mapcs0 = 1,
  184. .odt_wr_mapcs0 = 1,
  185. .wlmrd = 40,
  186. .wldqsen = 25,
  187. };
  188. const int row_diff = 1;
  189. #else /* Unknown PCM052 variant */
  190. #error DDR characteristics undefined for this target. Please define them.
  191. #endif
  192. ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings,
  193. pcm052_phy_settings, 1, row_diff);
  194. gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  195. return 0;
  196. }
  197. static void clock_init(void)
  198. {
  199. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  200. struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
  201. clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
  202. CCM_CCGR0_UART1_CTRL_MASK);
  203. clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
  204. CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
  205. clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
  206. CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
  207. CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
  208. CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK |
  209. CCM_CCGR2_QSPI0_CTRL_MASK);
  210. clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
  211. CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
  212. clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
  213. CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
  214. CCM_CCGR4_GPC_CTRL_MASK);
  215. clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
  216. CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
  217. clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
  218. CCM_CCGR7_SDHC1_CTRL_MASK);
  219. clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
  220. CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
  221. clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
  222. CCM_CCGR10_NFC_CTRL_MASK);
  223. clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
  224. ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
  225. clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
  226. ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
  227. clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
  228. CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
  229. clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK,
  230. CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN |
  231. CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN |
  232. CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN |
  233. CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN |
  234. CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) |
  235. CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4));
  236. clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
  237. CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
  238. CCM_CACRR_ARM_CLK_DIV(0));
  239. clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
  240. CCM_CSCMR1_ESDHC1_CLK_SEL(3) |
  241. CCM_CSCMR1_QSPI0_CLK_SEL(3) |
  242. CCM_CSCMR1_NFC_CLK_SEL(0));
  243. clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
  244. CCM_CSCDR1_RMII_CLK_EN);
  245. clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
  246. CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
  247. CCM_CSCDR2_NFC_EN);
  248. clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
  249. CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) |
  250. CCM_CSCDR3_QSPI0_X2_DIV(1) |
  251. CCM_CSCDR3_QSPI0_X4_DIV(3) |
  252. CCM_CSCDR3_NFC_PRE_DIV(5));
  253. clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
  254. CCM_CSCMR2_RMII_CLK_SEL(0));
  255. }
  256. static void mscm_init(void)
  257. {
  258. struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
  259. int i;
  260. for (i = 0; i < MSCM_IRSPRC_NUM; i++)
  261. writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
  262. }
  263. int board_early_init_f(void)
  264. {
  265. clock_init();
  266. mscm_init();
  267. return 0;
  268. }
  269. int board_init(void)
  270. {
  271. struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR;
  272. /* address of boot parameters */
  273. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  274. /*
  275. * Enable external 32K Oscillator
  276. *
  277. * The internal clock experiences significant drift
  278. * so we must use the external oscillator in order
  279. * to maintain correct time in the hwclock
  280. */
  281. setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
  282. return 0;
  283. }
  284. #ifdef CONFIG_TARGET_BK4R1
  285. void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
  286. {
  287. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  288. struct fuse_bank *bank = &ocotp->bank[4];
  289. struct fuse_bank4_regs *fuse =
  290. (struct fuse_bank4_regs *)bank->fuse_regs;
  291. u32 value;
  292. /*
  293. * BK4 has different layout of stored MAC address
  294. * than one used in imx_get_mac_from_fuse() @ generic.c
  295. */
  296. switch (dev_id) {
  297. case 0:
  298. value = readl(&fuse->mac_addr1);
  299. mac[0] = value >> 8;
  300. mac[1] = value;
  301. value = readl(&fuse->mac_addr0);
  302. mac[2] = value >> 24;
  303. mac[3] = value >> 16;
  304. mac[4] = value >> 8;
  305. mac[5] = value;
  306. break;
  307. case 1:
  308. value = readl(&fuse->mac_addr2);
  309. mac[0] = value >> 24;
  310. mac[1] = value >> 16;
  311. mac[2] = value >> 8;
  312. mac[3] = value;
  313. value = readl(&fuse->mac_addr1);
  314. mac[4] = value >> 24;
  315. mac[5] = value >> 16;
  316. break;
  317. }
  318. }
  319. int board_late_init(void)
  320. {
  321. struct src *psrc = (struct src *)SRC_BASE_ADDR;
  322. u32 reg;
  323. if (IS_ENABLED(CONFIG_LED))
  324. led_default_state();
  325. /*
  326. * BK4r1 handle emergency/service SD card boot
  327. * Checking the SBMR1 register BOOTCFG1 byte:
  328. * NAND:
  329. * bit [2] - NAND data width - 16
  330. * bit [5] - NAND fast boot
  331. * bit [7] = 1 - NAND as a source of booting
  332. * SD card (0x64):
  333. * bit [4] = 0 - SD card source
  334. * bit [6] = 1 - SD/MMC source
  335. */
  336. reg = readl(&psrc->sbmr1);
  337. if ((reg & SRC_SBMR1_BOOTCFG1_SDMMC) &&
  338. !(reg & SRC_SBMR1_BOOTCFG1_MMC)) {
  339. printf("------ SD card boot -------\n");
  340. env_set_default("!LVFBootloader", 0);
  341. env_set("bootcmd",
  342. "run prepare_install_bk4r1_envs; run install_bk4r1rs");
  343. }
  344. return 0;
  345. }
  346. /**
  347. * KSZ8081
  348. */
  349. #define MII_KSZ8081_REFERENCE_CLOCK_SELECT 0x1f
  350. #define RMII_50MHz_CLOCK 0x8180
  351. int board_phy_config(struct phy_device *phydev)
  352. {
  353. /* Set 50 MHz reference clock */
  354. phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ8081_REFERENCE_CLOCK_SELECT,
  355. RMII_50MHz_CLOCK);
  356. return genphy_config(phydev);
  357. }
  358. #endif /* CONFIG_TARGET_BK4R1 */
  359. int checkboard(void)
  360. {
  361. #ifdef CONFIG_TARGET_BK4R1
  362. u32 *gpio3_pdir = (u32 *)(GPIO3_BASE_ADDR + 0x10);
  363. /*
  364. * USB_RESET_N (PTC30 - GPIO103 - PORT3[7]):
  365. * L333 -> pull up added -> read 1
  366. * L320 -> no pull up -> read 0
  367. *
  368. * Default iomuxc_ptc30 value after reset: 0x300061 -> RCON28
  369. * - input enabled, pull (up/down) disabled
  370. */
  371. if (*gpio3_pdir & BIT(7))
  372. puts("Board: BK4r1 (L333)\n");
  373. else
  374. puts("Board: BK4r1 (L320)\n");
  375. #else
  376. puts("Board: PCM-052\n");
  377. #endif
  378. return 0;
  379. }