max77620_init.h 1.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2013-2015
  4. * NVIDIA Corporation <www.nvidia.com>
  5. */
  6. #ifndef _MAX77620_INIT_H_
  7. #define _MAX77620_INIT_H_
  8. /* MAX77620-PMIC-specific early init regs */
  9. #define MAX77620_I2C_ADDR 0x78
  10. #define MAX77620_I2C_ADDR_7BIT 0x3C
  11. #define MAX77620_CNFGGLBL1_REG 0x00
  12. #define MAX77620_SD0_REG 0x16
  13. #define MAX77620_SD1_REG 0x17
  14. #define MAX77620_SD2_REG 0x18
  15. #define MAX77620_SD3_REG 0x19
  16. #define MAX77620_CNFG2SD_REG 0x22
  17. #define MAX77620_CNFG1_L0_REG 0x23
  18. #define MAX77620_CNFG2_L0_REG 0x24
  19. #define MAX77620_CNFG1_L1_REG 0x25
  20. #define MAX77620_CNFG2_L1_REG 0x26
  21. #define MAX77620_CNFG1_L2_REG 0x27
  22. #define MAX77620_CNFG2_L2_REG 0x28
  23. #define MAX77620_CNFG1_L3_REG 0x29
  24. #define MAX77620_CNFG2_L3_REG 0x2A
  25. #define MAX77620_CNFG1_L4_REG 0x2B
  26. #define MAX77620_CNFG2_L4_REG 0x2C
  27. #define MAX77620_CNFG1_L5_REG 0x2D
  28. #define MAX77620_CNFG2_L5_REG 0x2E
  29. #define MAX77620_CNFG1_L6_REG 0x2F
  30. #define MAX77620_CNFG2_L6_REG 0x30
  31. #define MAX77620_CNFG1_L7_REG 0x31
  32. #define MAX77620_CNFG2_L7_REG 0x32
  33. #define MAX77620_CNFG1_L8_REG 0x33
  34. #define MAX77620_CNFG2_L8_REG 0x34
  35. #define MAX77620_CNFG3_LDO_REG 0x35
  36. #define MAX77620_GPIO0_REG 0x36
  37. #define MAX77620_GPIO1_REG 0x37
  38. #define MAX77620_GPIO2_REG 0x38
  39. #define MAX77620_GPIO3_REG 0x39
  40. #define MAX77620_GPIO4_REG 0x3A
  41. #define MAX77620_GPIO5_REG 0x3B
  42. #define MAX77620_GPIO6_REG 0x3C
  43. #define MAX77620_GPIO7_REG 0x3D
  44. #define MAX77620_GPIO_PUE_GPIO 0x3E
  45. #define MAX77620_GPIO_PDE_GPIO 0x3F
  46. #define MAX77620_AME_GPIO 0x40
  47. #define MAX77620_REG_ONOFF_CFG1 0x41
  48. #define MAX77620_REG_ONOFF_CFG2 0x42
  49. #define MAX77620_CID0_REG 0x58
  50. #define MAX77620_CID1_REG 0x59
  51. #define MAX77620_CID2_REG 0x5A
  52. #define MAX77620_CID3_REG 0x5B
  53. #define MAX77620_CID4_REG 0x5C
  54. #define MAX77620_CID5_REG 0x5D
  55. #define I2C_SEND_2_BYTES 0x0A02
  56. void pmic_enable_cpu_vdd(void);
  57. #endif /* _MAX77620_INIT_H_ */