imx6logic.c 8.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Logic PD, Inc.
  4. *
  5. * Author: Adam Ford <aford173@gmail.com>
  6. *
  7. * Based on SabreSD by Fabio Estevam <fabio.estevam@nxp.com>
  8. * and updates by Jagan Teki <jagan@amarulasolutions.com>
  9. */
  10. #include <common.h>
  11. #include <env.h>
  12. #include <init.h>
  13. #include <miiphy.h>
  14. #include <input.h>
  15. #include <mmc.h>
  16. #include <fsl_esdhc_imx.h>
  17. #include <serial.h>
  18. #include <asm/global_data.h>
  19. #include <asm/io.h>
  20. #include <asm/gpio.h>
  21. #include <linux/sizes.h>
  22. #include <asm/arch/clock.h>
  23. #include <asm/arch/crm_regs.h>
  24. #include <asm/arch/iomux.h>
  25. #include <asm/arch/mxc_hdmi.h>
  26. #include <asm/arch/mx6-pins.h>
  27. #include <asm/arch/sys_proto.h>
  28. #include <asm/mach-imx/boot_mode.h>
  29. #include <asm/mach-imx/iomux-v3.h>
  30. DECLARE_GLOBAL_DATA_PTR;
  31. #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  32. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  33. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  34. #define NAND_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  35. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  36. PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  37. int dram_init(void)
  38. {
  39. gd->ram_size = imx_ddr_size();
  40. return 0;
  41. }
  42. static iomux_v3_cfg_t const nand_pads[] = {
  43. MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  44. MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
  45. MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
  46. MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  47. MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  48. MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  49. MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  50. MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  51. MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  52. MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  53. MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  54. MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  55. MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  56. MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  57. MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  58. };
  59. static void setup_nand_pins(void)
  60. {
  61. imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
  62. }
  63. static int ar8031_phy_fixup(struct phy_device *phydev)
  64. {
  65. unsigned short val;
  66. /* To enable AR8031 output a 125MHz clk from CLK_25M */
  67. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
  68. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
  69. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
  70. val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
  71. val &= 0xffe3;
  72. val |= 0x18;
  73. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
  74. /* introduce tx clock delay */
  75. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
  76. val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
  77. val |= 0x0100;
  78. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
  79. return 0;
  80. }
  81. int board_phy_config(struct phy_device *phydev)
  82. {
  83. ar8031_phy_fixup(phydev);
  84. if (phydev->drv->config)
  85. phydev->drv->config(phydev);
  86. return 0;
  87. }
  88. /*
  89. * Do not overwrite the console
  90. * Use always serial for U-Boot console
  91. */
  92. int overwrite_console(void)
  93. {
  94. return 1;
  95. }
  96. int board_early_init_f(void)
  97. {
  98. setup_nand_pins();
  99. return 0;
  100. }
  101. int board_init(void)
  102. {
  103. /* address of boot parameters */
  104. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  105. return 0;
  106. }
  107. int board_late_init(void)
  108. {
  109. env_set("board_name", "imx6logic");
  110. if (is_mx6dq()) {
  111. env_set("board_rev", "MX6DQ");
  112. if (!env_get("fdt_file"))
  113. env_set("fdt_file", "imx6q-logicpd.dtb");
  114. }
  115. return 0;
  116. }
  117. #ifdef CONFIG_SPL_BUILD
  118. #include <asm/arch/mx6-ddr.h>
  119. #include <asm/arch/mx6q-ddr.h>
  120. #include <spl.h>
  121. #include <linux/libfdt.h>
  122. #ifdef CONFIG_SPL_OS_BOOT
  123. int spl_start_uboot(void)
  124. {
  125. /* break into full u-boot on 'c' */
  126. if (serial_tstc() && serial_getc() == 'c')
  127. return 1;
  128. return 0;
  129. }
  130. #endif
  131. void board_boot_order(u32 *spl_boot_list)
  132. {
  133. struct src *psrc = (struct src *)SRC_BASE_ADDR;
  134. unsigned int reg = readl(&psrc->sbmr1) >> 11;
  135. u32 boot_mode = imx6_src_get_boot_mode() & IMX6_BMODE_MASK;
  136. unsigned int bmode = readl(&src_base->sbmr2);
  137. /* If bmode is serial or USB phy is active, return serial */
  138. if (((bmode >> 24) & 0x03) == 0x01 || is_usbotg_phy_active()) {
  139. spl_boot_list[0] = BOOT_DEVICE_BOARD;
  140. return;
  141. }
  142. switch (boot_mode >> IMX6_BMODE_SHIFT) {
  143. case IMX6_BMODE_NAND_MIN ... IMX6_BMODE_NAND_MAX:
  144. spl_boot_list[0] = BOOT_DEVICE_NAND;
  145. break;
  146. case IMX6_BMODE_SD:
  147. case IMX6_BMODE_ESD:
  148. case IMX6_BMODE_MMC:
  149. case IMX6_BMODE_EMMC:
  150. /*
  151. * Upon reading BOOT_CFG register the following map is done:
  152. * Bit 11 and 12 of BOOT_CFG register can determine the current
  153. * mmc port
  154. * 0x1 SD1-SOM
  155. * 0x2 SD2-Baseboard
  156. */
  157. reg &= 0x3; /* Only care about bottom 2 bits */
  158. switch (reg) {
  159. case 0:
  160. spl_boot_list[0] = BOOT_DEVICE_MMC1;
  161. break;
  162. case 1:
  163. spl_boot_list[0] = BOOT_DEVICE_MMC2;
  164. break;
  165. }
  166. break;
  167. default:
  168. /* By default use USB downloader */
  169. spl_boot_list[0] = BOOT_DEVICE_BOARD;
  170. break;
  171. }
  172. /* As a last resort, use serial downloader */
  173. spl_boot_list[1] = BOOT_DEVICE_BOARD;
  174. }
  175. static void ccgr_init(void)
  176. {
  177. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  178. writel(0x00C03F3F, &ccm->CCGR0);
  179. writel(0x0030FC03, &ccm->CCGR1);
  180. writel(0x0FFFC000, &ccm->CCGR2);
  181. writel(0x3FF00000, &ccm->CCGR3);
  182. writel(0xFFFFF300, &ccm->CCGR4);
  183. writel(0x0F0000F3, &ccm->CCGR5);
  184. writel(0x00000FFF, &ccm->CCGR6);
  185. }
  186. static int mx6q_dcd_table[] = {
  187. MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
  188. MX6_IOM_GRP_DDRPKE, 0x00000000,
  189. MX6_IOM_DRAM_SDCLK_0, 0x00000030,
  190. MX6_IOM_DRAM_SDCLK_1, 0x00000030,
  191. MX6_IOM_DRAM_CAS, 0x00000030,
  192. MX6_IOM_DRAM_RAS, 0x00000030,
  193. MX6_IOM_GRP_ADDDS, 0x00000030,
  194. MX6_IOM_DRAM_RESET, 0x00000030,
  195. MX6_IOM_DRAM_SDBA2, 0x00000000,
  196. MX6_IOM_DRAM_SDODT0, 0x00000030,
  197. MX6_IOM_DRAM_SDODT1, 0x00000030,
  198. MX6_IOM_GRP_CTLDS, 0x00000030,
  199. MX6_IOM_DDRMODE_CTL, 0x00020000,
  200. MX6_IOM_DRAM_SDQS0, 0x00000030,
  201. MX6_IOM_DRAM_SDQS1, 0x00000030,
  202. MX6_IOM_DRAM_SDQS2, 0x00000030,
  203. MX6_IOM_DRAM_SDQS3, 0x00000030,
  204. MX6_IOM_GRP_DDRMODE, 0x00020000,
  205. MX6_IOM_GRP_B0DS, 0x00000030,
  206. MX6_IOM_GRP_B1DS, 0x00000030,
  207. MX6_IOM_GRP_B2DS, 0x00000030,
  208. MX6_IOM_GRP_B3DS, 0x00000030,
  209. MX6_IOM_DRAM_DQM0, 0x00000030,
  210. MX6_IOM_DRAM_DQM1, 0x00000030,
  211. MX6_IOM_DRAM_DQM2, 0x00000030,
  212. MX6_IOM_DRAM_DQM3, 0x00000030,
  213. MX6_MMDC_P0_MDSCR, 0x00008000,
  214. MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
  215. MX6_MMDC_P0_MPWLDECTRL0, 0x002D003A,
  216. MX6_MMDC_P0_MPWLDECTRL1, 0x0038002B,
  217. MX6_MMDC_P0_MPDGCTRL0, 0x03340338,
  218. MX6_MMDC_P0_MPDGCTRL1, 0x0334032C,
  219. MX6_MMDC_P0_MPRDDLCTL, 0x4036383C,
  220. MX6_MMDC_P0_MPWRDLCTL, 0x2E384038,
  221. MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
  222. MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
  223. MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
  224. MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
  225. MX6_MMDC_P0_MPMUR0, 0x00000800,
  226. MX6_MMDC_P0_MDPDC, 0x00020036,
  227. MX6_MMDC_P0_MDOTC, 0x09444040,
  228. MX6_MMDC_P0_MDCFG0, 0xB8BE7955,
  229. MX6_MMDC_P0_MDCFG1, 0xFF328F64,
  230. MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
  231. MX6_MMDC_P0_MDMISC, 0x00011740,
  232. MX6_MMDC_P0_MDSCR, 0x00008000,
  233. MX6_MMDC_P0_MDRWD, 0x000026D2,
  234. MX6_MMDC_P0_MDOR, 0x00BE1023,
  235. MX6_MMDC_P0_MDASP, 0x00000047,
  236. MX6_MMDC_P0_MDCTL, 0x85190000,
  237. MX6_MMDC_P0_MDSCR, 0x00888032,
  238. MX6_MMDC_P0_MDSCR, 0x00008033,
  239. MX6_MMDC_P0_MDSCR, 0x00008031,
  240. MX6_MMDC_P0_MDSCR, 0x19408030,
  241. MX6_MMDC_P0_MDSCR, 0x04008040,
  242. MX6_MMDC_P0_MDREF, 0x00007800,
  243. MX6_MMDC_P0_MPODTCTRL, 0x00000007,
  244. MX6_MMDC_P0_MDPDC, 0x00025576,
  245. MX6_MMDC_P0_MAPSR, 0x00011006,
  246. MX6_MMDC_P0_MDSCR, 0x00000000,
  247. /* enable AXI cache for VDOA/VPU/IPU */
  248. MX6_IOMUXC_GPR4, 0xF00000CF,
  249. /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
  250. MX6_IOMUXC_GPR6, 0x007F007F,
  251. MX6_IOMUXC_GPR7, 0x007F007F,
  252. };
  253. static void ddr_init(int *table, int size)
  254. {
  255. int i;
  256. for (i = 0; i < size / 2 ; i++)
  257. writel(table[2 * i + 1], table[2 * i]);
  258. }
  259. static void spl_dram_init(void)
  260. {
  261. if (is_mx6dq())
  262. ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
  263. }
  264. void board_init_f(ulong dummy)
  265. {
  266. /* DDR initialization */
  267. spl_dram_init();
  268. /* setup AIPS and disable watchdog */
  269. arch_cpu_init();
  270. ccgr_init();
  271. gpr_init();
  272. /* iomux and setup of uart and NAND pins */
  273. board_early_init_f();
  274. /* setup GP timer */
  275. timer_init();
  276. /* Enable device tree and early DM support*/
  277. spl_early_init();
  278. /* UART clocks enabled and gd valid - init serial console */
  279. preloader_console_init();
  280. }
  281. #endif