spl.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Wandboard
  4. * Author: Tungyi Lin <tungyilin1127@gmail.com>
  5. * Richard Hu <hakahu@gmail.com>
  6. */
  7. #include <image.h>
  8. #include <init.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/imx-regs.h>
  11. #include <asm/arch/iomux.h>
  12. #include <asm/arch/mx6-pins.h>
  13. #include <errno.h>
  14. #include <asm/gpio.h>
  15. #include <asm/mach-imx/iomux-v3.h>
  16. #include <asm/mach-imx/video.h>
  17. #include <mmc.h>
  18. #include <fsl_esdhc_imx.h>
  19. #include <asm/arch/crm_regs.h>
  20. #include <asm/io.h>
  21. #include <asm/arch/sys_proto.h>
  22. #include <serial.h>
  23. #include <spl.h>
  24. #include <linux/delay.h>
  25. #include <asm/arch/mx6-ddr.h>
  26. /*
  27. * Driving strength:
  28. * 0x30 == 40 Ohm
  29. * 0x28 == 48 Ohm
  30. */
  31. #define IMX6DQ_DRIVE_STRENGTH 0x30
  32. #define IMX6SDL_DRIVE_STRENGTH 0x28
  33. /* configure MX6Q/DUAL mmdc DDR io registers */
  34. static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
  35. .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
  36. .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
  37. .dram_cas = IMX6DQ_DRIVE_STRENGTH,
  38. .dram_ras = IMX6DQ_DRIVE_STRENGTH,
  39. .dram_reset = IMX6DQ_DRIVE_STRENGTH,
  40. .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
  41. .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
  42. .dram_sdba2 = 0x00000000,
  43. .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
  44. .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
  45. .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
  46. .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
  47. .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
  48. .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
  49. .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
  50. .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
  51. .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
  52. .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
  53. .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
  54. .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
  55. .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
  56. .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
  57. .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
  58. .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
  59. .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
  60. .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
  61. };
  62. /* configure MX6Q/DUAL mmdc GRP io registers */
  63. static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
  64. .grp_ddr_type = 0x000c0000,
  65. .grp_ddrmode_ctl = 0x00020000,
  66. .grp_ddrpke = 0x00000000,
  67. .grp_addds = IMX6DQ_DRIVE_STRENGTH,
  68. .grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
  69. .grp_ddrmode = 0x00020000,
  70. .grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
  71. .grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
  72. .grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
  73. .grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
  74. .grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
  75. .grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
  76. .grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
  77. .grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
  78. };
  79. /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
  80. struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
  81. .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
  82. .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
  83. .dram_cas = IMX6SDL_DRIVE_STRENGTH,
  84. .dram_ras = IMX6SDL_DRIVE_STRENGTH,
  85. .dram_reset = IMX6SDL_DRIVE_STRENGTH,
  86. .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
  87. .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
  88. .dram_sdba2 = 0x00000000,
  89. .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
  90. .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
  91. .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
  92. .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
  93. .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
  94. .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
  95. .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
  96. .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
  97. .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
  98. .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
  99. .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
  100. .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
  101. .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
  102. .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
  103. .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
  104. .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
  105. .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
  106. .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
  107. };
  108. /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
  109. struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
  110. .grp_ddr_type = 0x000c0000,
  111. .grp_ddrmode_ctl = 0x00020000,
  112. .grp_ddrpke = 0x00000000,
  113. .grp_addds = IMX6SDL_DRIVE_STRENGTH,
  114. .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
  115. .grp_ddrmode = 0x00020000,
  116. .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
  117. .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
  118. .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
  119. .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
  120. .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
  121. .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
  122. .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
  123. .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
  124. };
  125. /* H5T04G63AFR-PB */
  126. static struct mx6_ddr3_cfg h5t04g63afr = {
  127. .mem_speed = 1600,
  128. .density = 4,
  129. .width = 16,
  130. .banks = 8,
  131. .rowaddr = 15,
  132. .coladdr = 10,
  133. .pagesz = 2,
  134. .trcd = 1375,
  135. .trcmin = 4875,
  136. .trasmin = 3500,
  137. };
  138. /* H5TQ2G63DFR-H9 */
  139. static struct mx6_ddr3_cfg h5tq2g63dfr = {
  140. .mem_speed = 1333,
  141. .density = 2,
  142. .width = 16,
  143. .banks = 8,
  144. .rowaddr = 14,
  145. .coladdr = 10,
  146. .pagesz = 2,
  147. .trcd = 1350,
  148. .trcmin = 4950,
  149. .trasmin = 3600,
  150. };
  151. static struct mx6_mmdc_calibration mx6q_2g_mmdc_calib = {
  152. .p0_mpwldectrl0 = 0x001f001f,
  153. .p0_mpwldectrl1 = 0x001f001f,
  154. .p1_mpwldectrl0 = 0x001f001f,
  155. .p1_mpwldectrl1 = 0x001f001f,
  156. .p0_mpdgctrl0 = 0x4301030d,
  157. .p0_mpdgctrl1 = 0x03020277,
  158. .p1_mpdgctrl0 = 0x4300030a,
  159. .p1_mpdgctrl1 = 0x02780248,
  160. .p0_mprddlctl = 0x4536393b,
  161. .p1_mprddlctl = 0x36353441,
  162. .p0_mpwrdlctl = 0x41414743,
  163. .p1_mpwrdlctl = 0x462f453f,
  164. };
  165. /* DDR 64bit 2GB */
  166. static struct mx6_ddr_sysinfo mem_q = {
  167. .dsize = 2,
  168. .cs1_mirror = 0,
  169. /* config for full 4GB range so that get_mem_size() works */
  170. .cs_density = 32,
  171. .ncs = 1,
  172. .bi_on = 1,
  173. .rtt_nom = 1,
  174. .rtt_wr = 0,
  175. .ralat = 5,
  176. .walat = 0,
  177. .mif3_mode = 3,
  178. .rst_to_cke = 0x23,
  179. .sde_to_rst = 0x10,
  180. };
  181. static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
  182. .p0_mpwldectrl0 = 0x001f001f,
  183. .p0_mpwldectrl1 = 0x001f001f,
  184. .p1_mpwldectrl0 = 0x001f001f,
  185. .p1_mpwldectrl1 = 0x001f001f,
  186. .p0_mpdgctrl0 = 0x420e020e,
  187. .p0_mpdgctrl1 = 0x02000200,
  188. .p1_mpdgctrl0 = 0x42020202,
  189. .p1_mpdgctrl1 = 0x01720172,
  190. .p0_mprddlctl = 0x494c4f4c,
  191. .p1_mprddlctl = 0x4a4c4c49,
  192. .p0_mpwrdlctl = 0x3f3f3133,
  193. .p1_mpwrdlctl = 0x39373f2e,
  194. };
  195. static struct mx6_mmdc_calibration mx6s_512m_mmdc_calib = {
  196. .p0_mpwldectrl0 = 0x0040003c,
  197. .p0_mpwldectrl1 = 0x0032003e,
  198. .p0_mpdgctrl0 = 0x42350231,
  199. .p0_mpdgctrl1 = 0x021a0218,
  200. .p0_mprddlctl = 0x4b4b4e49,
  201. .p0_mpwrdlctl = 0x3f3f3035,
  202. };
  203. /* DDR 64bit 1GB */
  204. static struct mx6_ddr_sysinfo mem_dl = {
  205. .dsize = 2,
  206. .cs1_mirror = 0,
  207. /* config for full 4GB range so that get_mem_size() works */
  208. .cs_density = 32,
  209. .ncs = 1,
  210. .bi_on = 1,
  211. .rtt_nom = 1,
  212. .rtt_wr = 0,
  213. .ralat = 5,
  214. .walat = 0,
  215. .mif3_mode = 3,
  216. .rst_to_cke = 0x23,
  217. .sde_to_rst = 0x10,
  218. };
  219. /* DDR 32bit 512MB */
  220. static struct mx6_ddr_sysinfo mem_s = {
  221. .dsize = 1,
  222. .cs1_mirror = 0,
  223. /* config for full 4GB range so that get_mem_size() works */
  224. .cs_density = 32,
  225. .ncs = 1,
  226. .bi_on = 1,
  227. .rtt_nom = 1,
  228. .rtt_wr = 0,
  229. .ralat = 5,
  230. .walat = 0,
  231. .mif3_mode = 3,
  232. .rst_to_cke = 0x23,
  233. .sde_to_rst = 0x10,
  234. };
  235. static void ccgr_init(void)
  236. {
  237. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  238. writel(0x00C03F3F, &ccm->CCGR0);
  239. writel(0x0030FC03, &ccm->CCGR1);
  240. writel(0x0FFFC000, &ccm->CCGR2);
  241. writel(0x3FF00000, &ccm->CCGR3);
  242. writel(0x00FFF300, &ccm->CCGR4);
  243. writel(0x0F0000C3, &ccm->CCGR5);
  244. writel(0x000003FF, &ccm->CCGR6);
  245. }
  246. static void spl_dram_init(void)
  247. {
  248. if (is_cpu_type(MXC_CPU_MX6SOLO)) {
  249. mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
  250. mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63dfr);
  251. } else if (is_cpu_type(MXC_CPU_MX6DL)) {
  252. mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
  253. mx6_dram_cfg(&mem_dl, &mx6dl_1g_mmdc_calib, &h5tq2g63dfr);
  254. } else if (is_cpu_type(MXC_CPU_MX6Q)) {
  255. mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
  256. mx6_dram_cfg(&mem_q, &mx6q_2g_mmdc_calib, &h5t04g63afr);
  257. }
  258. udelay(100);
  259. }
  260. static void setup_spi(void)
  261. {
  262. enable_spi_clk(true, 2);
  263. }
  264. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  265. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  266. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  267. static iomux_v3_cfg_t const uart1_pads[] = {
  268. IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  269. IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  270. };
  271. static void setup_iomux_uart(void)
  272. {
  273. SETUP_IOMUX_PADS(uart1_pads);
  274. }
  275. void board_init_f(ulong dummy)
  276. {
  277. ccgr_init();
  278. /* setup AIPS and disable watchdog */
  279. arch_cpu_init();
  280. gpr_init();
  281. /* iomux */
  282. setup_iomux_uart();
  283. /* setup GP timer */
  284. timer_init();
  285. /* UART clocks enabled and gd valid - init serial console */
  286. preloader_console_init();
  287. /* enable ECSPI clocks */
  288. setup_spi();
  289. /* DDR initialization */
  290. spl_dram_init();
  291. }
  292. void board_boot_order(u32 *spl_boot_list)
  293. {
  294. switch (spl_boot_device()) {
  295. case BOOT_DEVICE_MMC2:
  296. case BOOT_DEVICE_MMC1:
  297. spl_boot_list[0] = BOOT_DEVICE_MMC2;
  298. spl_boot_list[1] = BOOT_DEVICE_MMC1;
  299. break;
  300. case BOOT_DEVICE_NOR:
  301. spl_boot_list[0] = BOOT_DEVICE_NOR;
  302. break;
  303. }
  304. }
  305. #ifdef CONFIG_SPL_LOAD_FIT
  306. int board_fit_config_name_match(const char *name)
  307. {
  308. return 0;
  309. }
  310. #endif
  311. #ifdef CONFIG_SPL_OS_BOOT
  312. int spl_start_uboot(void)
  313. {
  314. char s[16];
  315. int ret;
  316. /*
  317. * We use BOOT_DEVICE_MMC1, but SD card is connected
  318. * to MMC2
  319. *
  320. * Correct "mapping" is delivered in board defined
  321. * board_boot_order() function.
  322. *
  323. * SD card boot is regarded as a "development" one,
  324. * hence we _always_ go through the u-boot.
  325. *
  326. */
  327. if (spl_boot_device() == BOOT_DEVICE_MMC1)
  328. return 1;
  329. /* break into full u-boot on 'c' */
  330. if (serial_tstc() && serial_getc() == 'c')
  331. return 1;
  332. env_init();
  333. ret = env_get_f("boot_os", s, sizeof(s));
  334. if ((ret != -1) && (strcmp(s, "no") == 0))
  335. return 1;
  336. /*
  337. * Check if SWUpdate recovery needs to be started
  338. *
  339. * recovery_status = NULL (not set - ret == -1) -> normal operation
  340. *
  341. * recovery_status = progress or
  342. * recovery_status = failed or
  343. * recovery_status = <any value> -> start SWUpdate
  344. *
  345. */
  346. ret = env_get_f("recovery_status", s, sizeof(s));
  347. if (ret != -1)
  348. return 1;
  349. return 0;
  350. }
  351. #endif /* CONFIG_SPL_OS_BOOT */
  352. #define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  353. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  354. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  355. #define NOR_WP IMX_GPIO_NR(1, 1)
  356. static iomux_v3_cfg_t const eimnor_pads[] = {
  357. IOMUX_PADS(PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  358. IOMUX_PADS(PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  359. IOMUX_PADS(PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  360. IOMUX_PADS(PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  361. IOMUX_PADS(PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  362. IOMUX_PADS(PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  363. IOMUX_PADS(PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  364. IOMUX_PADS(PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  365. IOMUX_PADS(PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  366. IOMUX_PADS(PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  367. IOMUX_PADS(PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  368. IOMUX_PADS(PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  369. IOMUX_PADS(PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  370. IOMUX_PADS(PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  371. IOMUX_PADS(PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  372. IOMUX_PADS(PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  373. IOMUX_PADS(PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  374. IOMUX_PADS(PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  375. IOMUX_PADS(PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  376. IOMUX_PADS(PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  377. IOMUX_PADS(PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  378. IOMUX_PADS(PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  379. IOMUX_PADS(PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  380. IOMUX_PADS(PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  381. IOMUX_PADS(PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  382. IOMUX_PADS(PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  383. IOMUX_PADS(PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  384. IOMUX_PADS(PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  385. IOMUX_PADS(PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  386. IOMUX_PADS(PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  387. IOMUX_PADS(PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  388. IOMUX_PADS(PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  389. IOMUX_PADS(PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  390. IOMUX_PADS(PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  391. IOMUX_PADS(PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  392. IOMUX_PADS(PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  393. IOMUX_PADS(PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  394. IOMUX_PADS(PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  395. IOMUX_PADS(PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  396. IOMUX_PADS(PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  397. IOMUX_PADS(PAD_EIM_A24__EIM_ADDR24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  398. IOMUX_PADS(PAD_EIM_A25__EIM_ADDR25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  399. IOMUX_PADS(PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  400. IOMUX_PADS(PAD_EIM_RW__EIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL)),
  401. IOMUX_PADS(PAD_EIM_CS0__EIM_CS0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  402. IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  403. };
  404. static void eimnor_cs_setup(void)
  405. {
  406. struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
  407. /* NOR configuration */
  408. writel(0x00620181, &weim_regs->cs0gcr1);
  409. writel(0x00000001, &weim_regs->cs0gcr2);
  410. writel(0x0b020000, &weim_regs->cs0rcr1);
  411. writel(0x0000b000, &weim_regs->cs0rcr2);
  412. writel(0x0804a240, &weim_regs->cs0wcr1);
  413. writel(0x00000000, &weim_regs->cs0wcr2);
  414. writel(0x00000120, &weim_regs->wcr);
  415. writel(0x00000010, &weim_regs->wiar);
  416. writel(0x00000000, &weim_regs->ear);
  417. set_chipselect_size(CS0_128);
  418. }
  419. static void setup_eimnor(void)
  420. {
  421. SETUP_IOMUX_PADS(eimnor_pads);
  422. gpio_direction_output(NOR_WP, 1);
  423. enable_eim_clk(1);
  424. eimnor_cs_setup();
  425. }
  426. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  427. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  428. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  429. #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
  430. static iomux_v3_cfg_t const usdhc2_pads[] = {
  431. IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  432. IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  433. IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  434. IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  435. IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  436. IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  437. /* Carrier MicroSD Card Detect */
  438. IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  439. };
  440. static iomux_v3_cfg_t const usdhc3_pads[] = {
  441. IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  442. IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  443. IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  444. IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  445. IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  446. IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  447. IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  448. IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  449. IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  450. IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  451. IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  452. };
  453. static struct fsl_esdhc_cfg usdhc_cfg[2] = {
  454. {USDHC3_BASE_ADDR},
  455. {USDHC2_BASE_ADDR},
  456. };
  457. int board_mmc_getcd(struct mmc *mmc)
  458. {
  459. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  460. int ret = 0;
  461. switch (cfg->esdhc_base) {
  462. case USDHC2_BASE_ADDR:
  463. ret = !gpio_get_value(USDHC2_CD_GPIO);
  464. break;
  465. case USDHC3_BASE_ADDR:
  466. /*
  467. * eMMC don't have card detect pin - since it is soldered to the
  468. * PCB board
  469. */
  470. ret = 1;
  471. break;
  472. }
  473. return ret;
  474. }
  475. int board_mmc_init(struct bd_info *bis)
  476. {
  477. int ret;
  478. u32 index = 0;
  479. /*
  480. * MMC MAP
  481. * (U-Boot device node) (Physical Port)
  482. * mmc0 Soldered on board eMMC device
  483. * mmc1 MicroSD card
  484. */
  485. for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
  486. switch (index) {
  487. case 0:
  488. SETUP_IOMUX_PADS(usdhc3_pads);
  489. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  490. usdhc_cfg[0].max_bus_width = 8;
  491. break;
  492. case 1:
  493. SETUP_IOMUX_PADS(usdhc2_pads);
  494. usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  495. usdhc_cfg[1].max_bus_width = 4;
  496. gpio_direction_input(USDHC2_CD_GPIO);
  497. break;
  498. default:
  499. printf("Warning: More USDHC controllers (%d) than supported (%d)\n",
  500. index + 1, CONFIG_SYS_FSL_USDHC_NUM);
  501. return -EINVAL;
  502. }
  503. ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
  504. if (ret)
  505. return ret;
  506. }
  507. return 0;
  508. }
  509. #ifdef CONFIG_SPL_BOARD_INIT
  510. #define DISPLAY_EN IMX_GPIO_NR(1, 2)
  511. void spl_board_init(void)
  512. {
  513. setup_eimnor();
  514. gpio_direction_output(DISPLAY_EN, 1);
  515. }
  516. #endif /* CONFIG_SPL_BOARD_INIT */