ddr.c 2.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. * Copyright 2020 Hitachi Power Grids. All rights reserved.
  5. */
  6. #include <common.h>
  7. #include <fsl_ddr_sdram.h>
  8. #include <fsl_ddr_dimm_params.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/global_data.h>
  12. #include <asm/arch/ls102xa_soc.h>
  13. DECLARE_GLOBAL_DATA_PTR;
  14. void fsl_ddr_board_options(memctl_options_t *popts,
  15. dimm_params_t *pdimm,
  16. unsigned int ctrl_num)
  17. {
  18. if (ctrl_num > 1) {
  19. printf("Not supported controller number %d\n", ctrl_num);
  20. return;
  21. }
  22. // 1/2 DRAM cycle (should be increased in case of ADDR/CMD heavily loaded than the clock)
  23. popts->clk_adjust = 0x4;
  24. popts->write_data_delay = 0x4;
  25. // wr leveling start value for lane 0
  26. popts->wrlvl_start = 0x5;
  27. // wr leveling start values for lanes 1-3 (lane 4 not there)
  28. popts->wrlvl_ctl_2 = 0x05050500;
  29. // 32-bit DRAM, no need to set start values for lanes we do not have (5-8)
  30. popts->wrlvl_ctl_3 = 0x0;
  31. popts->cpo_override = 0x1f;
  32. /* force DDR bus width to 32 bits */
  33. popts->data_bus_width = 1;
  34. popts->otf_burst_chop_en = 0;
  35. popts->burst_length = DDR_BL8;
  36. /*
  37. * Factors to consider for half-strength driver enable:
  38. * - number of DIMMs installed
  39. */
  40. popts->half_strength_driver_enable = 1;
  41. /*
  42. * Write leveling override
  43. */
  44. popts->wrlvl_override = 1;
  45. popts->wrlvl_sample = 0xf;
  46. /*
  47. * Rtt and Rtt_WR override
  48. */
  49. popts->rtt_override = 0;
  50. /* Enable ZQ calibration */
  51. popts->zq_en = 1;
  52. popts->cswl_override = DDR_CSWL_CS0;
  53. /* optimize cpo for erratum A-009942 */
  54. popts->cpo_sample = 0x58;
  55. /* DHC_EN =1, ODT = 75 Ohm */
  56. popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
  57. popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
  58. }
  59. int fsl_initdram(void)
  60. {
  61. phys_size_t dram_size;
  62. puts("Initializing DDR....using SPD\n");
  63. dram_size = fsl_ddr_sdram();
  64. erratum_a008850_post();
  65. gd->ram_size = dram_size;
  66. return 0;
  67. }
  68. int dram_init_banksize(void)
  69. {
  70. gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  71. gd->bd->bi_dram[0].size = gd->ram_size;
  72. return 0;
  73. }