tlb.c 3.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016 Keymile AG
  4. * Rainer Boschung <rainer.boschung@keymile.com>
  5. *
  6. * Copyright 2013 Freescale Semiconductor, Inc.
  7. */
  8. #include <asm/mmu.h>
  9. #include <asm/u-boot.h>
  10. struct fsl_e_tlb_entry tlb_table[] = {
  11. /* TLB 0 - for temp stack in cache */
  12. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
  13. CONFIG_SYS_INIT_RAM_ADDR_PHYS,
  14. MAS3_SX | MAS3_SW | MAS3_SR, 0,
  15. 0, 0, BOOKE_PAGESZ_4K, 0),
  16. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  17. CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
  18. MAS3_SX | MAS3_SW | MAS3_SR, 0,
  19. 0, 0, BOOKE_PAGESZ_4K, 0),
  20. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  21. CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
  22. MAS3_SX | MAS3_SW | MAS3_SR, 0,
  23. 0, 0, BOOKE_PAGESZ_4K, 0),
  24. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  25. CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
  26. MAS3_SX | MAS3_SW | MAS3_SR, 0,
  27. 0, 0, BOOKE_PAGESZ_4K, 0),
  28. /* TLB 1 */
  29. /* *I*** - Covers boot page */
  30. SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
  31. MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
  32. 0, 0, BOOKE_PAGESZ_4K, 1),
  33. /* *I*G* - CCSRBAR */
  34. SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  35. MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
  36. 0, 1, BOOKE_PAGESZ_16M, 1),
  37. /* *I*G* - Flash, localbus */
  38. /* This will be changed to *I*G* after relocation to RAM. */
  39. SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
  40. MAS3_SX | MAS3_SR, MAS2_W | MAS2_G,
  41. 0, 2, BOOKE_PAGESZ_128M, 1),
  42. /* *I*G* - PCI1 */
  43. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
  44. MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
  45. 0, 3, BOOKE_PAGESZ_1G, 1),
  46. /* *I*G* - PCI1 I/O */
  47. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
  48. MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
  49. 0, 4, BOOKE_PAGESZ_256K, 1),
  50. /* Bman/Qman */
  51. SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
  52. MAS3_SX | MAS3_SW | MAS3_SR, 0,
  53. 0, 5, BOOKE_PAGESZ_16M, 1),
  54. SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
  55. CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
  56. MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
  57. 0, 6, BOOKE_PAGESZ_16M, 1),
  58. SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
  59. MAS3_SX | MAS3_SW | MAS3_SR, 0,
  60. 0, 7, BOOKE_PAGESZ_16M, 1),
  61. SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
  62. CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
  63. MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
  64. 0, 8, BOOKE_PAGESZ_16M, 1),
  65. SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
  66. MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
  67. 0, 9, BOOKE_PAGESZ_4M, 1),
  68. /* *I*G - NAND */
  69. SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
  70. MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
  71. 0, 10, BOOKE_PAGESZ_64K, 1),
  72. /* QRIO */
  73. SET_TLB_ENTRY(1, CONFIG_SYS_QRIO_BASE, CONFIG_SYS_QRIO_BASE_PHYS,
  74. MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
  75. 0, 11, BOOKE_PAGESZ_64K, 1),
  76. /* MRAM */
  77. SET_TLB_ENTRY(1, CONFIG_SYS_MRAM_BASE, SYS_MRAM_BASE_PHYS,
  78. MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
  79. 0, 12, BOOKE_PAGESZ_128M, 1),
  80. /* BFTIC */
  81. SET_TLB_ENTRY(1, SYS_BFTIC_BASE, SYS_BFTIC_BASE_PHYS,
  82. MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
  83. 0, 13, BOOKE_PAGESZ_128M, 1),
  84. /*
  85. * entry 14 and 15 has been used hard coded, they will be disabled
  86. * in cpu_init_f, so do not use them here!!.
  87. */
  88. /* PAXE */
  89. SET_TLB_ENTRY(1, CONFIG_SYS_PAXE_BASE, SYS_PAXE_BASE_PHYS,
  90. MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
  91. 0, 16, BOOKE_PAGESZ_128M, 1)
  92. };
  93. int num_tlb_entries = ARRAY_SIZE(tlb_table);