kmcent2.c 8.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016 Keymile AG
  4. * Rainer Boschung <rainer.boschung@keymile.com>
  5. *
  6. * Copyright 2013 Freescale Semiconductor, Inc.
  7. */
  8. #include <asm/cache.h>
  9. #include <asm/fsl_fdt.h>
  10. #include <asm/fsl_law.h>
  11. #include <asm/fsl_liodn.h>
  12. #include <asm/fsl_portals.h>
  13. #include <asm/fsl_serdes.h>
  14. #include <asm/immap_85xx.h>
  15. #include <asm/mmu.h>
  16. #include <asm/processor.h>
  17. #include <fdt_support.h>
  18. #include <fm_eth.h>
  19. #include <hwconfig.h>
  20. #include <image.h>
  21. #include <linux/compiler.h>
  22. #include <net.h>
  23. #include <netdev.h>
  24. #include <vsc9953.h>
  25. #include "../common/common.h"
  26. #include "../common/qrio.h"
  27. DECLARE_GLOBAL_DATA_PTR;
  28. static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
  29. int checkboard(void)
  30. {
  31. printf("Board: Hitachi Power Grids %s\n", KM_BOARD_NAME);
  32. return 0;
  33. }
  34. #define RSTRQSR1_WDT_RR 0x00200000
  35. #define RSTRQSR1_SW_RR 0x00100000
  36. int board_early_init_f(void)
  37. {
  38. struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
  39. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  40. bool cpuwd_flag = false;
  41. /* board specific IFC configuration: increased bus turnaround time */
  42. setbits_be32(&ifc.gregs->ifc_gcr, 8 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
  43. /* configure mode for uP reset request */
  44. qrio_uprstreq(UPREQ_CORE_RST);
  45. /* board only uses the DDR_MCK0, so disable the DDR_MCK1 */
  46. setbits_be32(&gur->ddrclkdr, 0x40000000);
  47. /* set reset reason according CPU register */
  48. if ((gur->rstrqsr1 & (RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR)) ==
  49. RSTRQSR1_WDT_RR)
  50. cpuwd_flag = true;
  51. qrio_cpuwd_flag(cpuwd_flag);
  52. /* clear CPU bits by writing 1 */
  53. setbits_be32(&gur->rstrqsr1, RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR);
  54. /* configure PRST lines for the application: */
  55. /*
  56. * ETHSW_DDR_RST:
  57. * reset at power-up and unit reset only and enable WD on it
  58. */
  59. qrio_prstcfg(KM_ETHSW_DDR_RST, PRSTCFG_POWUP_UNIT_RST);
  60. qrio_wdmask(KM_ETHSW_DDR_RST, true);
  61. /*
  62. * XES_PHY_RST:
  63. * reset at power-up and unit reset only and enable WD on it
  64. */
  65. qrio_prstcfg(KM_XES_PHY_RST, PRSTCFG_POWUP_UNIT_RST);
  66. qrio_wdmask(KM_XES_PHY_RST, true);
  67. /*
  68. * ES_PHY_RST:
  69. * reset at power-up and unit reset only and enable WD on it
  70. */
  71. qrio_prstcfg(KM_ES_PHY_RST, PRSTCFG_POWUP_UNIT_RST);
  72. qrio_wdmask(KM_ES_PHY_RST, true);
  73. /*
  74. * EFE_RST:
  75. * reset at power-up and unit reset only and enable WD on it
  76. */
  77. qrio_prstcfg(KM_EFE_RST, PRSTCFG_POWUP_UNIT_RST);
  78. qrio_wdmask(KM_EFE_RST, true);
  79. /*
  80. * BFTIC4_RST:
  81. * reset at power-up and unit reset only and enable WD on it
  82. */
  83. qrio_prstcfg(KM_BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST);
  84. qrio_wdmask(KM_BFTIC4_RST, true);
  85. /*
  86. * DPAXE_RST:
  87. * reset at power-up and unit reset only and enable WD on it
  88. */
  89. qrio_prstcfg(KM_DPAXE_RST, PRSTCFG_POWUP_UNIT_RST);
  90. qrio_wdmask(KM_DPAXE_RST, true);
  91. /*
  92. * PEXSW_RST:
  93. * reset at power-up and unit reset only, deassert reset w/o WD
  94. */
  95. qrio_prstcfg(KM_PEXSW_RST, PRSTCFG_POWUP_UNIT_RST);
  96. qrio_prst(KM_PEXSW_RST, false, false);
  97. /*
  98. * PEXSW_NT_RST:
  99. * reset at power-up and unit reset only, deassert reset w/o WD
  100. */
  101. qrio_prstcfg(KM_PEXSW_NT_RST, PRSTCFG_POWUP_UNIT_RST);
  102. qrio_prst(KM_PEXSW_NT_RST, false, false);
  103. /*
  104. * BOBCAT_RST:
  105. * reset at power-up and unit reset only, deassert reset w/o WD
  106. */
  107. qrio_prstcfg(KM_BOBCAT_RST, PRSTCFG_POWUP_UNIT_RST);
  108. qrio_prst(KM_BOBCAT_RST, false, false);
  109. /*
  110. * FEMT_RST:
  111. * reset at power-up and unit reset only and enable WD
  112. */
  113. qrio_prstcfg(KM_FEMT_RST, PRSTCFG_POWUP_UNIT_RST);
  114. qrio_wdmask(KM_FEMT_RST, true);
  115. /*
  116. * FOAM_RST:
  117. * reset at power-up and unit reset only and enable WD
  118. */
  119. qrio_prstcfg(KM_FOAM_RST, PRSTCFG_POWUP_UNIT_RST);
  120. qrio_wdmask(KM_FOAM_RST, true);
  121. return 0;
  122. }
  123. int board_early_init_r(void)
  124. {
  125. int ret = 0;
  126. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  127. int flash_esel = find_tlb_idx((void *)flashbase, 1);
  128. /*
  129. * Remap Boot flash region to caching-inhibited
  130. * so that flash can be erased properly.
  131. */
  132. /* Flush d-cache and invalidate i-cache of any FLASH data */
  133. flush_dcache();
  134. invalidate_icache();
  135. if (flash_esel == -1) {
  136. /* very unlikely unless something is messed up */
  137. puts("Error: Could not find TLB for FLASH BASE\n");
  138. flash_esel = 2; /* give our best effort to continue */
  139. } else {
  140. /* invalidate existing TLB entry for flash */
  141. disable_tlb(flash_esel);
  142. }
  143. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
  144. MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
  145. 0, flash_esel, BOOKE_PAGESZ_256M, 1);
  146. set_liodns();
  147. setup_qbman_portals();
  148. qrio_set_leds();
  149. /* enable Application Buffer */
  150. qrio_enable_app_buffer();
  151. return ret;
  152. }
  153. unsigned long get_serial_clock(unsigned long dummy)
  154. {
  155. return (gd->bus_clk / 2);
  156. }
  157. unsigned long get_board_sys_clk(unsigned long dummy)
  158. {
  159. return 66666666;
  160. }
  161. int misc_init_f(void)
  162. {
  163. /* configure QRIO pis for i2c deblocking */
  164. i2c_deblock_gpio_cfg();
  165. /*
  166. * CFE_RST (front phy):
  167. * reset at power-up, unit and core reset, deasset reset w/o WD
  168. */
  169. qrio_prstcfg(KM_CFE_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
  170. qrio_prst(KM_CFE_RST, false, false);
  171. /*
  172. * ZL30158_RST (PTP clock generator):
  173. * reset at power-up only, deassert reset and enable WD on it
  174. */
  175. qrio_prstcfg(KM_ZL30158_RST, PRSTCFG_POWUP_RST);
  176. qrio_prst(KM_ZL30158_RST, false, false);
  177. /*
  178. * ZL30364_RST (EEC generator):
  179. * reset at power-up only, deassert reset and enable WD on it
  180. */
  181. qrio_prstcfg(KM_ZL30364_RST, PRSTCFG_POWUP_RST);
  182. qrio_prst(KM_ZL30364_RST, false, false);
  183. return 0;
  184. }
  185. #define USED_SRDS_BANK 0
  186. #define EXPECTED_SRDS_RFCK SRDS_PLLCR0_RFCK_SEL_100
  187. #define BRG01_IOCLK12 0x02000000
  188. #define EC2_GTX_CLK125 0x08000000
  189. int misc_init_r(void)
  190. {
  191. serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
  192. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_MPC85xx_SCFG;
  193. ccsr_gur_t __iomem *gur = (ccsr_gur_t __iomem *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  194. /* check SERDES bank 0 reference clock */
  195. u32 actual = in_be32(&regs->bank[USED_SRDS_BANK].pllcr0);
  196. if (actual & SRDS_PLLCR0_POFF)
  197. printf("Warning: SERDES bank %u pll is off\n", USED_SRDS_BANK);
  198. if ((actual & SRDS_PLLCR0_RFCK_SEL_MASK) != EXPECTED_SRDS_RFCK) {
  199. printf("Warning: SERDES bank %u expects %sMHz clock, is %sMHz\n",
  200. USED_SRDS_BANK,
  201. serdes_clock_to_string(EXPECTED_SRDS_RFCK),
  202. serdes_clock_to_string(actual));
  203. }
  204. /* QE IO clk : BRG01 is used over clk12 for HDLC clk (20 MhZ) */
  205. out_be32(&scfg->qeioclkcr,
  206. in_be32(&scfg->qeioclkcr) | BRG01_IOCLK12);
  207. ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
  208. CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
  209. /* Fix polarity of Card Detect and Write Protect */
  210. out_be32(&gur->sdhcpcr, 0xFFFFFFFF);
  211. /*
  212. * EC1 is disabled in our design, so we must explicitly set GTXCLKSEL
  213. * to EC2
  214. */
  215. out_be32(&scfg->emiiocr, in_be32(&scfg->emiiocr) | EC2_GTX_CLK125);
  216. return 0;
  217. }
  218. int hush_init_var(void)
  219. {
  220. ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
  221. return 0;
  222. }
  223. int last_stage_init(void)
  224. {
  225. const char *kmem;
  226. /* DIP switch support on BFTIC */
  227. struct bfticu_iomap *bftic4 =
  228. (struct bfticu_iomap *)SYS_BFTIC_BASE;
  229. u8 dip_switch = in_8((u8 *)&bftic4->mswitch) & BFTICU_DIPSWITCH_MASK;
  230. if (dip_switch != 0) {
  231. /* start bootloader */
  232. puts("DIP: Enabled\n");
  233. env_set("actual_bank", "0");
  234. }
  235. set_km_env();
  236. /*
  237. * bootm_size is used to fixup the FDT memory node
  238. * set it to kernelmem that has the same value
  239. */
  240. kmem = env_get("kernelmem");
  241. if (kmem)
  242. env_set("bootm_size", kmem);
  243. return 0;
  244. }
  245. void fdt_fixup_fman_mac_addresses(void *blob)
  246. {
  247. int node, ret;
  248. char path[24];
  249. unsigned char mac_addr[6];
  250. /*
  251. * Just the fm1-mac5 must be set by us, u-boot handle the 2 others,
  252. * get the mac addr from env
  253. */
  254. if (!eth_env_get_enetaddr_by_index("eth", 4, mac_addr)) {
  255. printf("eth4addr env variable not defined\n");
  256. return;
  257. }
  258. /* local management port */
  259. strcpy(path, "/soc/fman/ethernet@e8000");
  260. node = fdt_path_offset(blob, path);
  261. if (node < 0) {
  262. printf("no %s\n", path);
  263. return;
  264. }
  265. ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6);
  266. if (ret) {
  267. printf("%s\n\terror setting local-mac-address property\n",
  268. path);
  269. }
  270. }
  271. int ft_board_setup(void *blob, struct bd_info *bd)
  272. {
  273. phys_addr_t base;
  274. phys_size_t size;
  275. ft_cpu_setup(blob, bd);
  276. base = env_get_bootm_low();
  277. size = env_get_bootm_size();
  278. fdt_fixup_memory(blob, (u64)base, (u64)size);
  279. fdt_fixup_liodn(blob);
  280. fdt_fixup_fman_mac_addresses(blob);
  281. if (hwconfig("qe-tdm"))
  282. fdt_del_diu(blob);
  283. return 0;
  284. }
  285. /* DIC26_SELFTEST GPIO used to start factory test sw */
  286. #define SELFTEST_PORT QRIO_GPIO_A
  287. #define SELFTEST_PIN 0
  288. int post_hotkeys_pressed(void)
  289. {
  290. qrio_gpio_direction_input(SELFTEST_PORT, SELFTEST_PIN);
  291. return qrio_get_gpio(SELFTEST_PORT, SELFTEST_PIN);
  292. }