ddr.c 2.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016 Keymile AG
  4. * Rainer Boschung <rainer.boschung@keymile.com>
  5. *
  6. * Copyright 2013 Freescale Semiconductor, Inc.
  7. */
  8. #include <asm/fsl_law.h>
  9. #include <asm/mmu.h>
  10. #include <asm/mpc85xx_gpio.h>
  11. #include <fsl_ddr_sdram.h>
  12. #include <fsl_ddr_dimm_params.h>
  13. #include <hwconfig.h>
  14. #include <i2c.h>
  15. #include <init.h>
  16. DECLARE_GLOBAL_DATA_PTR;
  17. #define DQSn_POS(n) (3 - (((n) - 1) % 4)) * 8
  18. #define DQSn_START(n, start) ((start) << DQSn_POS(n))
  19. void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm,
  20. unsigned int ctrl_num)
  21. {
  22. if (ctrl_num > 1) {
  23. printf("Not supported controller number %d\n", ctrl_num);
  24. return;
  25. }
  26. /* 1/2 clk delay between wr command and data strobe */
  27. popts->write_data_delay = 4;
  28. /* clk lauched 1/2 applied cylcle after address command */
  29. popts->clk_adjust = 4;
  30. /* 1T timing: command/address held for only 1 cycle */
  31. popts->twot_en = 0;
  32. popts->threet_en = 0;
  33. /* optimize cpo for erratum A-009942 */
  34. popts->cpo_sample = 0x3b;
  35. /* we have only one module, half str should be OK */
  36. popts->half_strength_driver_enable = 1;
  37. /*
  38. * Write leveling override
  39. */
  40. /* set for DDR3-1600 */
  41. popts->wrlvl_override = 1;
  42. popts->wrlvl_sample = 0xf;
  43. popts->wrlvl_start = 0x7;
  44. /* DQS write leveling start time according layout */
  45. popts->wrlvl_ctl_2 = (DQSn_START(1, 0x06) |
  46. DQSn_START(2, 0x06) |
  47. DQSn_START(3, 0x07) |
  48. DQSn_START(4, 0x07));
  49. popts->wrlvl_ctl_3 = (DQSn_START(5, 0x07) |
  50. DQSn_START(6, 0x08) |
  51. DQSn_START(7, 0x08) |
  52. DQSn_START(8, 0x08));
  53. /*
  54. * rtt and wtt_wr override
  55. */
  56. popts->rtt_override = 0;
  57. /* Enable ZQ calibration */
  58. popts->zq_en = 1;
  59. /* DHC_EN =1, ODT = 75 Ohm */
  60. popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
  61. popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
  62. }
  63. int dram_init(void)
  64. {
  65. phys_size_t dram_size;
  66. puts("Initializing....using SPD\n");
  67. dram_size = fsl_ddr_sdram();
  68. dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  69. dram_size *= 0x100000;
  70. gd->ram_size = dram_size;
  71. return 0;
  72. }