km83xx.c 5.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2006 Freescale Semiconductor, Inc.
  4. * Dave Liu <daveliu@freescale.com>
  5. *
  6. * Copyright (C) 2007 Logic Product Development, Inc.
  7. * Peter Barada <peterb@logicpd.com>
  8. *
  9. * Copyright (C) 2007 MontaVista Software, Inc.
  10. * Anton Vorontsov <avorontsov@ru.mvista.com>
  11. *
  12. * (C) Copyright 2008 - 2010
  13. * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  14. */
  15. #include <common.h>
  16. #include <env.h>
  17. #include <fdt_support.h>
  18. #include <init.h>
  19. #include <ioports.h>
  20. #include <log.h>
  21. #include <mpc83xx.h>
  22. #include <i2c.h>
  23. #include <miiphy.h>
  24. #include <asm/global_data.h>
  25. #include <asm/io.h>
  26. #include <asm/mmu.h>
  27. #include <asm/processor.h>
  28. #include <pci.h>
  29. #include <linux/delay.h>
  30. #include <linux/libfdt.h>
  31. #include <post.h>
  32. #include "../common/common.h"
  33. DECLARE_GLOBAL_DATA_PTR;
  34. static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
  35. static int piggy_present(void)
  36. {
  37. struct km_bec_fpga __iomem *base =
  38. (struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE;
  39. return in_8(&base->bprth) & PIGGY_PRESENT;
  40. }
  41. int ethernet_present(void)
  42. {
  43. return piggy_present();
  44. }
  45. int board_early_init_r(void)
  46. {
  47. struct km_bec_fpga *base =
  48. (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
  49. #if defined(CONFIG_ARCH_MPC8360)
  50. unsigned short svid;
  51. /*
  52. * Because of errata in the UCCs, we have to write to the reserved
  53. * registers to slow the clocks down.
  54. */
  55. svid = SVR_REV(mfspr(SVR));
  56. switch (svid) {
  57. case 0x0020:
  58. /*
  59. * MPC8360ECE.pdf QE_ENET10 table 4:
  60. * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
  61. * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
  62. */
  63. setbits_be32((void *)(CONFIG_SYS_IMMR + 0x14a8), 0x0c003000);
  64. break;
  65. case 0x0021:
  66. /*
  67. * MPC8360ECE.pdf QE_ENET10 table 4:
  68. * IMMR + 0x14AC[24:27] = 1010
  69. */
  70. clrsetbits_be32((void *)(CONFIG_SYS_IMMR + 0x14ac),
  71. 0x00000050, 0x000000a0);
  72. break;
  73. }
  74. #endif
  75. /* enable the PHY on the PIGGY */
  76. setbits_8(&base->pgy_eth, 0x01);
  77. /* enable the Unit LED (green) */
  78. setbits_8(&base->oprth, WRL_BOOT);
  79. /* enable Application Buffer */
  80. setbits_8(&base->oprtl, OPRTL_XBUFENA);
  81. return 0;
  82. }
  83. int misc_init_r(void)
  84. {
  85. ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
  86. CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
  87. return 0;
  88. }
  89. int last_stage_init(void)
  90. {
  91. #if defined(CONFIG_TARGET_KMCOGE5NE)
  92. struct bfticu_iomap *base =
  93. (struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE;
  94. u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK;
  95. if (dip_switch != 0) {
  96. /* start bootloader */
  97. puts("DIP: Enabled\n");
  98. env_set("actual_bank", "0");
  99. }
  100. #endif
  101. set_km_env();
  102. return 0;
  103. }
  104. static int fixed_sdram(void)
  105. {
  106. immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  107. u32 msize = 0;
  108. u32 ddr_size;
  109. u32 ddr_size_log2;
  110. out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e));
  111. out_be32(&im->ddr.csbnds[0].csbnds, (CONFIG_SYS_DDR_CS0_BNDS) | 0x7f);
  112. out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
  113. out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
  114. out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
  115. out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
  116. out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
  117. out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
  118. out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
  119. out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
  120. out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
  121. out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
  122. out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
  123. udelay(200);
  124. setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
  125. msize = CONFIG_SYS_DDR_SIZE << 20;
  126. disable_addr_trans();
  127. msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
  128. enable_addr_trans();
  129. msize /= (1024 * 1024);
  130. if (CONFIG_SYS_DDR_SIZE != msize) {
  131. for (ddr_size = msize << 20, ddr_size_log2 = 0;
  132. (ddr_size > 1);
  133. ddr_size = ddr_size >> 1, ddr_size_log2++)
  134. if (ddr_size & 1)
  135. return -1;
  136. out_be32(&im->sysconf.ddrlaw[0].ar,
  137. (LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE)));
  138. out_be32(&im->ddr.csbnds[0].csbnds,
  139. (((msize / 16) - 1) & 0xff));
  140. }
  141. return msize;
  142. }
  143. int dram_init(void)
  144. {
  145. immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  146. u32 msize = 0;
  147. if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
  148. return -ENXIO;
  149. out_be32(&im->sysconf.ddrlaw[0].bar,
  150. CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR);
  151. msize = fixed_sdram();
  152. #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  153. /*
  154. * Initialize DDR ECC byte
  155. */
  156. ddr_enable_ecc(msize * 1024 * 1024);
  157. #endif
  158. /* return total bus SDRAM size(bytes) -- DDR */
  159. gd->ram_size = msize * 1024 * 1024;
  160. return 0;
  161. }
  162. int checkboard(void)
  163. {
  164. puts("Board: Hitachi " CONFIG_SYS_CONFIG_NAME);
  165. if (piggy_present())
  166. puts(" with PIGGY.");
  167. puts("\n");
  168. return 0;
  169. }
  170. int ft_board_setup(void *blob, struct bd_info *bd)
  171. {
  172. ft_cpu_setup(blob, bd);
  173. return 0;
  174. }
  175. #if defined(CONFIG_HUSH_INIT_VAR)
  176. int hush_init_var(void)
  177. {
  178. ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
  179. return 0;
  180. }
  181. #endif
  182. #if defined(CONFIG_POST)
  183. int post_hotkeys_pressed(void)
  184. {
  185. int testpin = 0;
  186. struct km_bec_fpga *base =
  187. (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
  188. int testpin_reg = in_8(&base->CONFIG_TESTPIN_REG);
  189. testpin = (testpin_reg & CONFIG_TESTPIN_MASK) != 0;
  190. debug("post_hotkeys_pressed: %d\n", !testpin);
  191. return testpin;
  192. }
  193. ulong post_word_load(void)
  194. {
  195. void* addr = (ulong *) (CPM_POST_WORD_ADDR);
  196. debug("post_word_load 0x%08lX: 0x%08X\n", (ulong)addr, in_le32(addr));
  197. return in_le32(addr);
  198. }
  199. void post_word_store(ulong value)
  200. {
  201. void* addr = (ulong *) (CPM_POST_WORD_ADDR);
  202. debug("post_word_store 0x%08lX: 0x%08lX\n", (ulong)addr, value);
  203. out_le32(addr, value);
  204. }
  205. int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
  206. {
  207. *vstart = CONFIG_SYS_MEMTEST_START;
  208. *size = CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START;
  209. debug("arch_memory_test_prepare 0x%08X 0x%08X\n", *vstart, *size);
  210. return 0;
  211. }
  212. #endif