malta.c 4.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
  4. * Copyright (C) 2013 Imagination Technologies
  5. */
  6. #include <config.h>
  7. #include <fdt_support.h>
  8. #include <ide.h>
  9. #include <init.h>
  10. #include <net.h>
  11. #include <netdev.h>
  12. #include <pci.h>
  13. #include <pci_gt64120.h>
  14. #include <pci_msc01.h>
  15. #include <rtc.h>
  16. #include <asm/global_data.h>
  17. #include <linux/delay.h>
  18. #include <asm/addrspace.h>
  19. #include <asm/io.h>
  20. #include <asm/malta.h>
  21. #include "superio.h"
  22. DECLARE_GLOBAL_DATA_PTR;
  23. #define MALTA_GT_PATH "/pci0@1be00000"
  24. #define MALTA_MSC_PATH "/pci0@1bd00000"
  25. enum core_card {
  26. CORE_UNKNOWN,
  27. CORE_LV,
  28. CORE_FPGA6,
  29. };
  30. enum sys_con {
  31. SYSCON_UNKNOWN,
  32. SYSCON_GT64120,
  33. SYSCON_MSC01,
  34. };
  35. static void malta_lcd_puts(const char *str)
  36. {
  37. int i;
  38. void *reg = (void *)CKSEG1ADDR(MALTA_ASCIIPOS0);
  39. /* print up to 8 characters of the string */
  40. for (i = 0; i < min((int)strlen(str), 8); i++) {
  41. __raw_writel(str[i], reg);
  42. reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
  43. }
  44. /* fill the rest of the display with spaces */
  45. for (; i < 8; i++) {
  46. __raw_writel(' ', reg);
  47. reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
  48. }
  49. }
  50. static enum core_card malta_core_card(void)
  51. {
  52. u32 corid, rev;
  53. const void *reg = (const void *)CKSEG1ADDR(MALTA_REVISION);
  54. rev = __raw_readl(reg);
  55. corid = (rev & MALTA_REVISION_CORID_MSK) >> MALTA_REVISION_CORID_SHF;
  56. switch (corid) {
  57. case MALTA_REVISION_CORID_CORE_LV:
  58. return CORE_LV;
  59. case MALTA_REVISION_CORID_CORE_FPGA6:
  60. return CORE_FPGA6;
  61. default:
  62. return CORE_UNKNOWN;
  63. }
  64. }
  65. static enum sys_con malta_sys_con(void)
  66. {
  67. switch (malta_core_card()) {
  68. case CORE_LV:
  69. return SYSCON_GT64120;
  70. case CORE_FPGA6:
  71. return SYSCON_MSC01;
  72. default:
  73. return SYSCON_UNKNOWN;
  74. }
  75. }
  76. int dram_init(void)
  77. {
  78. gd->ram_size = CONFIG_SYS_MEM_SIZE;
  79. return 0;
  80. }
  81. int checkboard(void)
  82. {
  83. enum core_card core;
  84. malta_lcd_puts("U-Boot");
  85. puts("Board: MIPS Malta");
  86. core = malta_core_card();
  87. switch (core) {
  88. case CORE_LV:
  89. puts(" CoreLV");
  90. break;
  91. case CORE_FPGA6:
  92. puts(" CoreFPGA6");
  93. break;
  94. default:
  95. puts(" CoreUnknown");
  96. }
  97. putc('\n');
  98. return 0;
  99. }
  100. #if !IS_ENABLED(CONFIG_DM_ETH)
  101. int board_eth_init(struct bd_info *bis)
  102. {
  103. return pci_eth_init(bis);
  104. }
  105. #endif
  106. void _machine_restart(void)
  107. {
  108. void __iomem *reset_base;
  109. reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE);
  110. __raw_writel(GORESET, reset_base);
  111. mdelay(1000);
  112. }
  113. int board_early_init_f(void)
  114. {
  115. ulong io_base;
  116. /* choose correct PCI I/O base */
  117. switch (malta_sys_con()) {
  118. case SYSCON_GT64120:
  119. io_base = CKSEG1ADDR(MALTA_GT_PCIIO_BASE);
  120. break;
  121. case SYSCON_MSC01:
  122. io_base = CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE);
  123. break;
  124. default:
  125. return -1;
  126. }
  127. set_io_port_base(io_base);
  128. /* setup FDC37M817 super I/O controller */
  129. malta_superio_init();
  130. return 0;
  131. }
  132. int misc_init_r(void)
  133. {
  134. rtc_reset();
  135. return 0;
  136. }
  137. #if IS_ENABLED(CONFIG_OF_BOARD_FIXUP)
  138. /*
  139. * TODO: currently doesn't work because rw_fdt_blob points to a
  140. * NOR flash address. This needs some changes in board_init_f.
  141. */
  142. int board_fix_fdt(void *rw_fdt_blob)
  143. {
  144. int node = -1;
  145. switch (malta_sys_con()) {
  146. case SYSCON_GT64120:
  147. node = fdt_path_offset(rw_fdt_blob, MALTA_GT_PATH);
  148. break;
  149. default:
  150. case SYSCON_MSC01:
  151. node = fdt_path_offset(rw_fdt_blob, MALTA_MSC_PATH);
  152. break;
  153. }
  154. return fdt_status_okay(rw_fdt_blob, node);
  155. }
  156. #endif
  157. int board_early_init_r(void)
  158. {
  159. struct udevice *dev;
  160. int ret;
  161. pci_init();
  162. ret = dm_pci_find_device(PCI_VENDOR_ID_INTEL,
  163. PCI_DEVICE_ID_INTEL_82371AB_0, 0, &dev);
  164. if (ret)
  165. panic("Failed to find PIIX4 PCI bridge\n");
  166. /* setup PCI interrupt routing */
  167. dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCA, 10);
  168. dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCB, 10);
  169. dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCC, 11);
  170. dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCD, 11);
  171. /* mux SERIRQ onto SERIRQ pin */
  172. dm_pci_clrset_config32(dev, PCI_CFG_PIIX4_GENCFG, 0,
  173. PCI_CFG_PIIX4_GENCFG_SERIRQ);
  174. /* enable SERIRQ - Linux currently depends upon this */
  175. dm_pci_clrset_config8(dev, PCI_CFG_PIIX4_SERIRQC, 0,
  176. PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT);
  177. ret = dm_pci_find_device(PCI_VENDOR_ID_INTEL,
  178. PCI_DEVICE_ID_INTEL_82371AB, 0, &dev);
  179. if (ret)
  180. panic("Failed to find PIIX4 IDE controller\n");
  181. /* enable bus master & IO access */
  182. dm_pci_clrset_config32(dev, PCI_COMMAND, 0,
  183. PCI_COMMAND_MASTER | PCI_COMMAND_IO);
  184. /* set latency */
  185. dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
  186. /* enable IDE/ATA */
  187. dm_pci_write_config32(dev, PCI_CFG_PIIX4_IDETIM_PRI,
  188. PCI_CFG_PIIX4_IDETIM_IDE);
  189. dm_pci_write_config32(dev, PCI_CFG_PIIX4_IDETIM_SEC,
  190. PCI_CFG_PIIX4_IDETIM_IDE);
  191. return 0;
  192. }