lowlevel_init.S 6.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
  4. */
  5. #include <config.h>
  6. #include <gt64120.h>
  7. #include <msc01.h>
  8. #include <pci.h>
  9. #include <asm/addrspace.h>
  10. #include <asm/asm.h>
  11. #include <asm/regdef.h>
  12. #include <asm/malta.h>
  13. #include <asm/mipsregs.h>
  14. #ifdef CONFIG_SYS_BIG_ENDIAN
  15. #define CPU_TO_GT32(_x) ((_x))
  16. #else
  17. #define CPU_TO_GT32(_x) ( \
  18. (((_x) & 0xff) << 24) | (((_x) & 0xff00) << 8) | \
  19. (((_x) & 0xff0000) >> 8) | (((_x) & 0xff000000) >> 24))
  20. #endif
  21. .text
  22. .set noreorder
  23. .globl lowlevel_init
  24. lowlevel_init:
  25. /* detect the core card */
  26. PTR_LI t0, CKSEG1ADDR(MALTA_REVISION)
  27. lw t0, 0(t0)
  28. srl t0, t0, MALTA_REVISION_CORID_SHF
  29. andi t0, t0, (MALTA_REVISION_CORID_MSK >> \
  30. MALTA_REVISION_CORID_SHF)
  31. /* core cards using the gt64120 system controller */
  32. li t1, MALTA_REVISION_CORID_CORE_LV
  33. beq t0, t1, _gt64120
  34. /* core cards using the MSC01 system controller */
  35. li t1, MALTA_REVISION_CORID_CORE_FPGA6
  36. beq t0, t1, _msc01
  37. nop
  38. /* unknown system controller */
  39. b .
  40. nop
  41. /*
  42. * Load BAR registers of GT64120 as done by YAMON
  43. *
  44. * based on a patch sent by Antony Pavlov <antonynpavlov@gmail.com>
  45. * to the barebox mailing list.
  46. * The subject of the original patch:
  47. * 'MIPS: qemu-malta: add YAMON-style GT64120 memory map'
  48. * URL:
  49. * http://www.mail-archive.com/barebox@lists.infradead.org/msg06128.html
  50. *
  51. * based on write_bootloader() in qemu.git/hw/mips_malta.c
  52. * see GT64120 manual and qemu.git/hw/gt64xxx.c for details
  53. */
  54. _gt64120:
  55. /* move GT64120 registers from 0x14000000 to 0x1be00000 */
  56. PTR_LI t1, CKSEG1ADDR(GT_DEF_BASE)
  57. li t0, CPU_TO_GT32(0xdf000000)
  58. sw t0, GT_ISD_OFS(t1)
  59. /* setup MEM-to-PCI0 mapping */
  60. PTR_LI t1, CKSEG1ADDR(MALTA_GT_BASE)
  61. /* setup PCI0 io window to 0x18000000-0x181fffff */
  62. li t0, CPU_TO_GT32(0xc0000000)
  63. sw t0, GT_PCI0IOLD_OFS(t1)
  64. li t0, CPU_TO_GT32(0x40000000)
  65. sw t0, GT_PCI0IOHD_OFS(t1)
  66. /* setup PCI0 mem windows */
  67. li t0, CPU_TO_GT32(0x80000000)
  68. sw t0, GT_PCI0M0LD_OFS(t1)
  69. li t0, CPU_TO_GT32(0x3f000000)
  70. sw t0, GT_PCI0M0HD_OFS(t1)
  71. li t0, CPU_TO_GT32(0xc1000000)
  72. sw t0, GT_PCI0M1LD_OFS(t1)
  73. li t0, CPU_TO_GT32(0x5e000000)
  74. sw t0, GT_PCI0M1HD_OFS(t1)
  75. jr ra
  76. nop
  77. /*
  78. *
  79. */
  80. _msc01:
  81. /* setup peripheral bus controller clock divide */
  82. PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_PBC_BASE)
  83. li t1, 0x1 << MSC01_PBC_CLKCFG_SHF
  84. sw t1, MSC01_PBC_CLKCFG_OFS(t0)
  85. /* tweak peripheral bus controller timings */
  86. li t1, (0x1 << MSC01_PBC_CS0TIM_CDT_SHF) | \
  87. (0x1 << MSC01_PBC_CS0TIM_CAT_SHF)
  88. sw t1, MSC01_PBC_CS0TIM_OFS(t0)
  89. li t1, (0x0 << MSC01_PBC_CS0RW_RDT_SHF) | \
  90. (0x2 << MSC01_PBC_CS0RW_RAT_SHF) | \
  91. (0x0 << MSC01_PBC_CS0RW_WDT_SHF) | \
  92. (0x2 << MSC01_PBC_CS0RW_WAT_SHF)
  93. sw t1, MSC01_PBC_CS0RW_OFS(t0)
  94. lw t1, MSC01_PBC_CS0CFG_OFS(t0)
  95. li t2, MSC01_PBC_CS0CFG_DTYP_MSK
  96. and t1, t2
  97. ori t1, (0x0 << MSC01_PBC_CS0CFG_ADM_SHF) | \
  98. (0x3 << MSC01_PBC_CS0CFG_WSIDLE_SHF) | \
  99. (0x10 << MSC01_PBC_CS0CFG_WS_SHF)
  100. sw t1, MSC01_PBC_CS0CFG_OFS(t0)
  101. /* setup basic address decode */
  102. PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_BIU_BASE)
  103. li t1, 0x0
  104. li t2, -CONFIG_SYS_MEM_SIZE
  105. sw t1, MSC01_BIU_MCBAS1L_OFS(t0)
  106. sw t2, MSC01_BIU_MCMSK1L_OFS(t0)
  107. sw t1, MSC01_BIU_MCBAS2L_OFS(t0)
  108. sw t2, MSC01_BIU_MCMSK2L_OFS(t0)
  109. /* initialise IP1 - unused */
  110. li t1, MALTA_MSC01_IP1_BASE
  111. li t2, -MALTA_MSC01_IP1_SIZE
  112. sw t1, MSC01_BIU_IP1BAS1L_OFS(t0)
  113. sw t2, MSC01_BIU_IP1MSK1L_OFS(t0)
  114. sw t1, MSC01_BIU_IP1BAS2L_OFS(t0)
  115. sw t2, MSC01_BIU_IP1MSK2L_OFS(t0)
  116. /* initialise IP2 - PCI */
  117. li t1, MALTA_MSC01_IP2_BASE1
  118. li t2, -MALTA_MSC01_IP2_SIZE1
  119. sw t1, MSC01_BIU_IP2BAS1L_OFS(t0)
  120. sw t2, MSC01_BIU_IP2MSK1L_OFS(t0)
  121. li t1, MALTA_MSC01_IP2_BASE2
  122. li t2, -MALTA_MSC01_IP2_SIZE2
  123. sw t1, MSC01_BIU_IP2BAS2L_OFS(t0)
  124. sw t2, MSC01_BIU_IP2MSK2L_OFS(t0)
  125. /* initialise IP3 - peripheral bus controller */
  126. li t1, MALTA_MSC01_IP3_BASE
  127. li t2, -MALTA_MSC01_IP3_SIZE
  128. sw t1, MSC01_BIU_IP3BAS1L_OFS(t0)
  129. sw t2, MSC01_BIU_IP3MSK1L_OFS(t0)
  130. sw t1, MSC01_BIU_IP3BAS2L_OFS(t0)
  131. sw t2, MSC01_BIU_IP3MSK2L_OFS(t0)
  132. /* setup PCI memory */
  133. PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_PCI_BASE)
  134. li t1, MALTA_MSC01_PCIMEM_BASE
  135. li t2, (-MALTA_MSC01_PCIMEM_SIZE) & MSC01_PCI_SC2PMMSKL_MSK_MSK
  136. li t3, MALTA_MSC01_PCIMEM_MAP
  137. sw t1, MSC01_PCI_SC2PMBASL_OFS(t0)
  138. sw t2, MSC01_PCI_SC2PMMSKL_OFS(t0)
  139. sw t3, MSC01_PCI_SC2PMMAPL_OFS(t0)
  140. /* setup PCI I/O */
  141. li t1, MALTA_MSC01_PCIIO_BASE
  142. li t2, (-MALTA_MSC01_PCIIO_SIZE) & MSC01_PCI_SC2PIOMSKL_MSK_MSK
  143. li t3, MALTA_MSC01_PCIIO_MAP
  144. sw t1, MSC01_PCI_SC2PIOBASL_OFS(t0)
  145. sw t2, MSC01_PCI_SC2PIOMSKL_OFS(t0)
  146. sw t3, MSC01_PCI_SC2PIOMAPL_OFS(t0)
  147. /* setup PCI_BAR0 memory window */
  148. li t1, -CONFIG_SYS_MEM_SIZE
  149. sw t1, MSC01_PCI_BAR0_OFS(t0)
  150. /* setup PCI to SysCon/CPU translation */
  151. sw t1, MSC01_PCI_P2SCMSKL_OFS(t0)
  152. sw zero, MSC01_PCI_P2SCMAPL_OFS(t0)
  153. /* setup PCI vendor & device IDs */
  154. li t1, (PCI_VENDOR_ID_MIPS << MSC01_PCI_HEAD0_VENDORID_SHF) | \
  155. (PCI_DEVICE_ID_MIPS_MSC01 << MSC01_PCI_HEAD0_DEVICEID_SHF)
  156. sw t1, MSC01_PCI_HEAD0_OFS(t0)
  157. /* setup PCI subsystem vendor & device IDs */
  158. sw t1, MSC01_PCI_HEAD11_OFS(t0)
  159. /* setup PCI class, revision */
  160. li t1, (PCI_CLASS_BRIDGE_HOST << MSC01_PCI_HEAD2_CLASS_SHF) | \
  161. (0x1 << MSC01_PCI_HEAD2_REV_SHF)
  162. sw t1, MSC01_PCI_HEAD2_OFS(t0)
  163. /* ensure a sane setup */
  164. sw zero, MSC01_PCI_HEAD3_OFS(t0)
  165. sw zero, MSC01_PCI_HEAD4_OFS(t0)
  166. sw zero, MSC01_PCI_HEAD5_OFS(t0)
  167. sw zero, MSC01_PCI_HEAD6_OFS(t0)
  168. sw zero, MSC01_PCI_HEAD7_OFS(t0)
  169. sw zero, MSC01_PCI_HEAD8_OFS(t0)
  170. sw zero, MSC01_PCI_HEAD9_OFS(t0)
  171. sw zero, MSC01_PCI_HEAD10_OFS(t0)
  172. sw zero, MSC01_PCI_HEAD12_OFS(t0)
  173. sw zero, MSC01_PCI_HEAD13_OFS(t0)
  174. sw zero, MSC01_PCI_HEAD14_OFS(t0)
  175. sw zero, MSC01_PCI_HEAD15_OFS(t0)
  176. /* setup PCI command register */
  177. li t1, (PCI_COMMAND_FAST_BACK | \
  178. PCI_COMMAND_SERR | \
  179. PCI_COMMAND_PARITY | \
  180. PCI_COMMAND_MASTER | \
  181. PCI_COMMAND_MEMORY)
  182. sw t1, MSC01_PCI_HEAD1_OFS(t0)
  183. /* setup PCI byte swapping */
  184. #ifdef CONFIG_SYS_BIG_ENDIAN
  185. li t1, (0x1 << MSC01_PCI_SWAP_BAR0_BSWAP_SHF) | \
  186. (0x1 << MSC01_PCI_SWAP_IO_BSWAP_SHF)
  187. sw t1, MSC01_PCI_SWAP_OFS(t0)
  188. #else
  189. sw zero, MSC01_PCI_SWAP_OFS(t0)
  190. #endif
  191. /* enable PCI host configuration cycles */
  192. lw t1, MSC01_PCI_CFG_OFS(t0)
  193. li t2, MSC01_PCI_CFG_RA_MSK | \
  194. MSC01_PCI_CFG_G_MSK | \
  195. MSC01_PCI_CFG_EN_MSK
  196. or t1, t1, t2
  197. sw t1, MSC01_PCI_CFG_OFS(t0)
  198. jr ra
  199. nop