ahci.c 5.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2012 Calxeda, Inc.
  4. */
  5. #include <common.h>
  6. #include <ahci.h>
  7. #include <asm/io.h>
  8. #include <linux/delay.h>
  9. #define CPHY_MAP(dev, addr) ((((dev) & 0x1f) << 7) | (((addr) >> 9) & 0x7f))
  10. #define CPHY_ADDR(base, dev, addr) ((base) | (((addr) & 0x1ff) << 2))
  11. #define CPHY_BASE 0xfff58000
  12. #define CPHY_WIDTH 0x1000
  13. #define CPHY_DTE_XS 5
  14. #define CPHY_MII 31
  15. #define SERDES_CR_CTL 0x80a0
  16. #define SERDES_CR_ADDR 0x80a1
  17. #define SERDES_CR_DATA 0x80a2
  18. #define CR_BUSY 0x0001
  19. #define CR_START 0x0001
  20. #define CR_WR_RDN 0x0002
  21. #define CPHY_TX_INPUT_STS 0x2001
  22. #define CPHY_RX_INPUT_STS 0x2002
  23. #define CPHY_SATA_TX_OVERRIDE_BIT 0x8000
  24. #define CPHY_SATA_RX_OVERRIDE_BIT 0x4000
  25. #define CPHY_TX_INPUT_OVERRIDE 0x2004
  26. #define CPHY_RX_INPUT_OVERRIDE 0x2005
  27. #define SPHY_LANE 0x100
  28. #define SPHY_HALF_RATE 0x0001
  29. #define CPHY_SATA_DPLL_MODE 0x0700
  30. #define CPHY_SATA_DPLL_SHIFT 8
  31. #define CPHY_SATA_TX_ATTEN 0x1c00
  32. #define CPHY_SATA_TX_ATTEN_SHIFT 10
  33. #define HB_SREG_SATA_ATTEN 0xfff3cf24
  34. #define SATA_PORT_BASE 0xffe08000
  35. #define SATA_VERSIONR 0xf8
  36. #define SATA_HB_VERSION 0x3332302a
  37. static u32 __combo_phy_reg_read(u8 phy, u8 dev, u32 addr)
  38. {
  39. u32 data;
  40. writel(CPHY_MAP(dev, addr), CPHY_BASE + 0x800 + CPHY_WIDTH * phy);
  41. data = readl(CPHY_ADDR(CPHY_BASE + CPHY_WIDTH * phy, dev, addr));
  42. return data;
  43. }
  44. static void __combo_phy_reg_write(u8 phy, u8 dev, u32 addr, u32 data)
  45. {
  46. writel(CPHY_MAP(dev, addr), CPHY_BASE + 0x800 + CPHY_WIDTH * phy);
  47. writel(data, CPHY_ADDR(CPHY_BASE + CPHY_WIDTH * phy, dev, addr));
  48. }
  49. static u32 combo_phy_read(u8 phy, u32 addr)
  50. {
  51. u8 dev = CPHY_DTE_XS;
  52. if (phy == 5)
  53. dev = CPHY_MII;
  54. while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY)
  55. udelay(5);
  56. __combo_phy_reg_write(phy, dev, SERDES_CR_ADDR, addr);
  57. __combo_phy_reg_write(phy, dev, SERDES_CR_CTL, CR_START);
  58. while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY)
  59. udelay(5);
  60. return __combo_phy_reg_read(phy, dev, SERDES_CR_DATA);
  61. }
  62. static void combo_phy_write(u8 phy, u32 addr, u32 data)
  63. {
  64. u8 dev = CPHY_DTE_XS;
  65. if (phy == 5)
  66. dev = CPHY_MII;
  67. while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY)
  68. udelay(5);
  69. __combo_phy_reg_write(phy, dev, SERDES_CR_ADDR, addr);
  70. __combo_phy_reg_write(phy, dev, SERDES_CR_DATA, data);
  71. __combo_phy_reg_write(phy, dev, SERDES_CR_CTL, CR_WR_RDN | CR_START);
  72. }
  73. static void cphy_spread_spectrum_override(u8 phy, u8 lane, u32 val)
  74. {
  75. u32 tmp;
  76. tmp = combo_phy_read(phy, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
  77. tmp &= ~CPHY_SATA_RX_OVERRIDE_BIT;
  78. combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
  79. tmp |= CPHY_SATA_RX_OVERRIDE_BIT;
  80. combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
  81. tmp &= ~CPHY_SATA_DPLL_MODE;
  82. tmp |= (val << CPHY_SATA_DPLL_SHIFT) & CPHY_SATA_DPLL_MODE;
  83. combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
  84. }
  85. static void cphy_tx_attenuation_override(u8 phy, u8 lane)
  86. {
  87. u32 val;
  88. u32 tmp;
  89. u8 shift;
  90. shift = ((phy == 5) ? 4 : lane) * 4;
  91. val = (readl(HB_SREG_SATA_ATTEN) >> shift) & 0xf;
  92. if (val & 0x8)
  93. return;
  94. tmp = combo_phy_read(phy, CPHY_TX_INPUT_STS + lane * SPHY_LANE);
  95. tmp &= ~CPHY_SATA_TX_OVERRIDE_BIT;
  96. combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
  97. tmp |= CPHY_SATA_TX_OVERRIDE_BIT;
  98. combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
  99. tmp |= (val << CPHY_SATA_TX_ATTEN_SHIFT) & CPHY_SATA_TX_ATTEN;
  100. combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
  101. }
  102. static void cphy_disable_port_overrides(u8 port)
  103. {
  104. u32 tmp;
  105. u8 lane = 0, phy = 0;
  106. if (port == 0)
  107. phy = 5;
  108. else if (port < 5)
  109. lane = port - 1;
  110. else
  111. return;
  112. tmp = combo_phy_read(phy, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
  113. tmp &= ~CPHY_SATA_RX_OVERRIDE_BIT;
  114. combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
  115. tmp = combo_phy_read(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE);
  116. tmp &= ~CPHY_SATA_TX_OVERRIDE_BIT;
  117. combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
  118. }
  119. void cphy_disable_overrides(void)
  120. {
  121. int i;
  122. u32 port_map;
  123. port_map = readl(0xffe08000 + HOST_PORTS_IMPL);
  124. for (i = 0; i < 5; i++) {
  125. if (port_map & (1 << i))
  126. cphy_disable_port_overrides(i);
  127. }
  128. }
  129. static void cphy_override_lane(u8 port)
  130. {
  131. u32 tmp, k = 0;
  132. u8 lane = 0, phy = 0;
  133. if (port == 0)
  134. phy = 5;
  135. else if (port < 5)
  136. lane = port - 1;
  137. else
  138. return;
  139. do {
  140. tmp = combo_phy_read(0, CPHY_RX_INPUT_STS +
  141. lane * SPHY_LANE);
  142. } while ((tmp & SPHY_HALF_RATE) && (k++ < 1000));
  143. cphy_spread_spectrum_override(phy, lane, 3);
  144. cphy_tx_attenuation_override(phy, lane);
  145. }
  146. #define WAIT_MS_LINKUP 4
  147. int ahci_link_up(struct ahci_uc_priv *probe_ent, int port)
  148. {
  149. u32 tmp;
  150. int j = 0;
  151. u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio;
  152. u32 is_highbank = readl(SATA_PORT_BASE + SATA_VERSIONR) ==
  153. SATA_HB_VERSION ? 1 : 0;
  154. /* Bring up SATA link.
  155. * SATA link bringup time is usually less than 1 ms; only very
  156. * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
  157. */
  158. while (j < WAIT_MS_LINKUP) {
  159. if (is_highbank && (j == 0)) {
  160. cphy_disable_port_overrides(port);
  161. writel(0x301, port_mmio + PORT_SCR_CTL);
  162. udelay(1000);
  163. writel(0x300, port_mmio + PORT_SCR_CTL);
  164. udelay(1000);
  165. cphy_override_lane(port);
  166. }
  167. tmp = readl(port_mmio + PORT_SCR_STAT);
  168. if ((tmp & 0xf) == 0x3)
  169. return 0;
  170. udelay(1000);
  171. j++;
  172. if ((j == WAIT_MS_LINKUP) && (tmp & 0xf))
  173. j = 0; /* retry phy reset */
  174. }
  175. return 1;
  176. }