veyron.c 2.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2015 Google, Inc
  4. */
  5. #include <clk.h>
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <init.h>
  9. #include <log.h>
  10. #include <asm/arch-rockchip/clock.h>
  11. #include <asm/global_data.h>
  12. #include <dt-bindings/clock/rk3288-cru.h>
  13. #include <linux/delay.h>
  14. #include <linux/err.h>
  15. #include <power/regulator.h>
  16. /*
  17. * We should increase the DDR voltage to 1.2V using the PWM regulator.
  18. * There is a U-Boot driver for this but it may need to add support for the
  19. * 'voltage-table' property.
  20. */
  21. #ifndef CONFIG_SPL_BUILD
  22. #if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
  23. static int veyron_init(void)
  24. {
  25. struct udevice *dev;
  26. struct clk clk;
  27. int ret;
  28. ret = regulator_get_by_platname("vdd_arm", &dev);
  29. if (ret) {
  30. debug("Cannot set regulator name\n");
  31. return ret;
  32. }
  33. /* Slowly raise to max CPU voltage to prevent overshoot */
  34. ret = regulator_set_value(dev, 1200000);
  35. if (ret)
  36. return ret;
  37. udelay(175); /* Must wait for voltage to stabilize, 2mV/us */
  38. ret = regulator_set_value(dev, 1400000);
  39. if (ret)
  40. return ret;
  41. udelay(100); /* Must wait for voltage to stabilize, 2mV/us */
  42. ret = rockchip_get_clk(&clk.dev);
  43. if (ret)
  44. return ret;
  45. clk.id = PLL_APLL;
  46. ret = clk_set_rate(&clk, 1800000000);
  47. if (IS_ERR_VALUE(ret))
  48. return ret;
  49. ret = regulator_get_by_platname("vcc33_sd", &dev);
  50. if (ret) {
  51. debug("Cannot get regulator name\n");
  52. return ret;
  53. }
  54. ret = regulator_set_value(dev, 3300000);
  55. if (ret)
  56. return ret;
  57. ret = regulators_enable_boot_on(false);
  58. if (ret) {
  59. debug("%s: Cannot enable boot on regulators\n", __func__);
  60. return ret;
  61. }
  62. return 0;
  63. }
  64. #endif
  65. int board_early_init_r(void)
  66. {
  67. struct udevice *dev;
  68. int ret;
  69. #if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
  70. if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) {
  71. ret = veyron_init();
  72. if (ret)
  73. return ret;
  74. }
  75. #endif
  76. /*
  77. * This init is done in SPL, but when chain-loading U-Boot SPL will
  78. * have been skipped. Allow the clock driver to check if it needs
  79. * setting up.
  80. */
  81. ret = rockchip_get_clk(&dev);
  82. if (ret) {
  83. debug("CLK init failed: %d\n", ret);
  84. return ret;
  85. }
  86. return 0;
  87. }
  88. #endif