sdram.c 2.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2007 Freescale Semiconductor, Inc.
  4. * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
  5. *
  6. * Authors: Nick.Spence@freescale.com
  7. * Wilson.Lo@freescale.com
  8. * scottwood@freescale.com
  9. *
  10. * This files is mostly identical to the original from
  11. * board\freescale\mpc8315erdb\sdram.c
  12. */
  13. #ifndef CONFIG_MPC83XX_SDRAM
  14. #include <common.h>
  15. #include <init.h>
  16. #include <mpc83xx.h>
  17. #include <spd_sdram.h>
  18. #include <asm/bitops.h>
  19. #include <asm/global_data.h>
  20. #include <asm/io.h>
  21. #include <asm/processor.h>
  22. DECLARE_GLOBAL_DATA_PTR;
  23. /* Fixed sdram init -- doesn't use serial presence detect.
  24. *
  25. * This is useful for faster booting in configs where the RAM is unlikely
  26. * to be changed, or for things like NAND booting where space is tight.
  27. */
  28. static long fixed_sdram(void)
  29. {
  30. immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  31. u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
  32. u32 msize_log2 = __ilog2(msize);
  33. out_be32(&im->sysconf.ddrlaw[0].bar,
  34. CONFIG_SYS_SDRAM_BASE & 0xfffff000);
  35. out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
  36. out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
  37. out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
  38. out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
  39. /* Currently we use only one CS, so disable the other bank. */
  40. out_be32(&im->ddr.cs_config[1], 0);
  41. out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
  42. out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
  43. out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
  44. out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
  45. out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
  46. out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
  47. out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
  48. out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
  49. out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
  50. out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
  51. sync();
  52. /* enable DDR controller */
  53. setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
  54. sync();
  55. return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
  56. }
  57. int dram_init(void)
  58. {
  59. immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  60. u32 msize;
  61. if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
  62. return -ENXIO;
  63. /* DDR SDRAM */
  64. msize = fixed_sdram();
  65. /* return total bus SDRAM size(bytes) -- DDR */
  66. gd->ram_size = msize;
  67. return 0;
  68. }
  69. #endif /* !CONFIG_MPC83XX_SDRAM */