mpc8308.c 2.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2014
  4. * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
  5. */
  6. #include <common.h>
  7. #include <command.h>
  8. #include <init.h>
  9. #include <asm/processor.h>
  10. #include <asm/io.h>
  11. #include <asm/global_data.h>
  12. #include <linux/delay.h>
  13. #include "mpc8308.h"
  14. #include <gdsys_fpga.h>
  15. #define REFLECTION_TESTPATTERN 0xdede
  16. #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
  17. #ifdef CONFIG_SYS_FPGA_NO_RFL_HI
  18. #define REFLECTION_TESTREG reflection_low
  19. #else
  20. #define REFLECTION_TESTREG reflection_high
  21. #endif
  22. DECLARE_GLOBAL_DATA_PTR;
  23. #ifdef CONFIG_GDSYS_LEGACY_DRIVERS
  24. /* as gpio output status cannot be read back, we have to buffer it locally */
  25. u32 gpio0_out;
  26. void setbits_gpio0_out(u32 mask)
  27. {
  28. immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  29. gpio0_out |= mask;
  30. out_be32(&immr->gpio[0].dat, gpio0_out);
  31. }
  32. void clrbits_gpio0_out(u32 mask)
  33. {
  34. immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  35. gpio0_out &= ~mask;
  36. out_be32(&immr->gpio[0].dat, gpio0_out);
  37. }
  38. int get_fpga_state(uint dev)
  39. {
  40. return gd->arch.fpga_state[dev];
  41. }
  42. int board_early_init_f(void)
  43. {
  44. uint k;
  45. for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
  46. gd->arch.fpga_state[k] = 0;
  47. return 0;
  48. }
  49. int board_early_init_r(void)
  50. {
  51. uint k;
  52. uint ctr;
  53. for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
  54. gd->arch.fpga_state[k] = 0;
  55. /*
  56. * reset FPGA
  57. */
  58. mpc8308_init();
  59. mpc8308_set_fpga_reset(1);
  60. mpc8308_setup_hw();
  61. for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
  62. ctr = 0;
  63. while (!mpc8308_get_fpga_done(k)) {
  64. mdelay(100);
  65. if (ctr++ > 5) {
  66. gd->arch.fpga_state[k] |=
  67. FPGA_STATE_DONE_FAILED;
  68. break;
  69. }
  70. }
  71. }
  72. udelay(10);
  73. mpc8308_set_fpga_reset(0);
  74. for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
  75. /*
  76. * wait for fpga out of reset
  77. */
  78. ctr = 0;
  79. while (1) {
  80. u16 val;
  81. FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN);
  82. FPGA_GET_REG(k, REFLECTION_TESTREG, &val);
  83. if (val == REFLECTION_TESTPATTERN_INV)
  84. break;
  85. mdelay(100);
  86. if (ctr++ > 5) {
  87. gd->arch.fpga_state[k] |=
  88. FPGA_STATE_REFLECTION_FAILED;
  89. break;
  90. }
  91. }
  92. }
  93. return 0;
  94. }
  95. #endif