spl.c 6.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2021 Gateworks Corporation
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <hang.h>
  8. #include <i2c.h>
  9. #include <image.h>
  10. #include <init.h>
  11. #include <log.h>
  12. #include <spl.h>
  13. #include <asm/io.h>
  14. #include <asm/mach-imx/gpio.h>
  15. #include <asm/mach-imx/iomux-v3.h>
  16. #include <asm/arch/clock.h>
  17. #include <asm/arch/imx8mm_pins.h>
  18. #include <asm/arch/sys_proto.h>
  19. #include <asm/mach-imx/boot_mode.h>
  20. #include <asm/arch/ddr.h>
  21. #include <asm-generic/gpio.h>
  22. #include <dm/uclass.h>
  23. #include <dm/device.h>
  24. #include <dm/uclass-internal.h>
  25. #include <dm/device-internal.h>
  26. #include <power/bd71837.h>
  27. #include <power/mp5416.h>
  28. #include "gsc.h"
  29. #include "lpddr4_timing.h"
  30. #define PCIE_RSTN IMX_GPIO_NR(4, 6)
  31. DECLARE_GLOBAL_DATA_PTR;
  32. static void spl_dram_init(int size)
  33. {
  34. struct dram_timing_info *dram_timing;
  35. switch (size) {
  36. case 1:
  37. dram_timing = &dram_timing_1gb;
  38. break;
  39. case 2:
  40. dram_timing = &dram_timing_2gb;
  41. break;
  42. case 4:
  43. dram_timing = &dram_timing_4gb;
  44. break;
  45. default:
  46. printf("Unknown DDR configuration: %d GiB\n", size);
  47. dram_timing = &dram_timing_1gb;
  48. size = 1;
  49. }
  50. printf("DRAM : LPDDR4 %d GiB\n", size);
  51. ddr_init(dram_timing);
  52. writel(size, M4_BOOTROM_BASE_ADDR);
  53. }
  54. #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
  55. #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
  56. static iomux_v3_cfg_t const uart_pads[] = {
  57. IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  58. IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  59. };
  60. static iomux_v3_cfg_t const wdog_pads[] = {
  61. IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  62. };
  63. int board_early_init_f(void)
  64. {
  65. struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  66. imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  67. set_wdog_reset(wdog);
  68. imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  69. return 0;
  70. }
  71. /*
  72. * Model specific PMIC adjustments necessary prior to DRAM init
  73. *
  74. * Note that we can not use pmic dm drivers here as we have a generic
  75. * venice dt that does not have board-specific pmic's defined.
  76. *
  77. * Instead we must use dm_i2c so we a helpers to give us
  78. * clrsetbit functions we would otherwise have if we could use PMIC dm
  79. * drivers.
  80. */
  81. static int dm_i2c_clrsetbits(struct udevice *dev, uint reg, uint clr, uint set)
  82. {
  83. int ret;
  84. u8 val;
  85. ret = dm_i2c_read(dev, reg, &val, 1);
  86. if (ret)
  87. return ret;
  88. val = (val & ~clr) | set;
  89. return dm_i2c_write(dev, reg, &val, 1);
  90. }
  91. static int power_init_board(void)
  92. {
  93. const char *model = gsc_get_model();
  94. struct udevice *bus;
  95. struct udevice *dev;
  96. int ret;
  97. if ((!strncmp(model, "GW71", 4)) ||
  98. (!strncmp(model, "GW72", 4)) ||
  99. (!strncmp(model, "GW73", 4))) {
  100. ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus);
  101. if (ret) {
  102. printf("PMIC : failed I2C1 probe: %d\n", ret);
  103. return ret;
  104. }
  105. ret = dm_i2c_probe(bus, 0x69, 0, &dev);
  106. if (ret) {
  107. printf("PMIC : failed probe: %d\n", ret);
  108. return ret;
  109. }
  110. puts("PMIC : MP5416\n");
  111. /* set VDD_ARM SW3 to 0.92V for 1.6GHz */
  112. dm_i2c_reg_write(dev, MP5416_VSET_SW3,
  113. BIT(7) | MP5416_VSET_SW3_SVAL(920000));
  114. }
  115. else if ((!strncmp(model, "GW7901", 6)) ||
  116. (!strncmp(model, "GW7902", 6))) {
  117. if (!strncmp(model, "GW7901", 6))
  118. ret = uclass_get_device_by_seq(UCLASS_I2C, 1, &bus);
  119. else
  120. ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus);
  121. if (ret) {
  122. printf("PMIC : failed I2C2 probe: %d\n", ret);
  123. return ret;
  124. }
  125. ret = dm_i2c_probe(bus, 0x4b, 0, &dev);
  126. if (ret) {
  127. printf("PMIC : failed probe: %d\n", ret);
  128. return ret;
  129. }
  130. puts("PMIC : BD71847\n");
  131. /* unlock the PMIC regs */
  132. dm_i2c_reg_write(dev, BD718XX_REGLOCK, 0x1);
  133. /* set switchers to forced PWM mode */
  134. dm_i2c_clrsetbits(dev, BD718XX_BUCK1_CTRL, 0, 0x8);
  135. dm_i2c_clrsetbits(dev, BD718XX_BUCK2_CTRL, 0, 0x8);
  136. dm_i2c_clrsetbits(dev, BD718XX_1ST_NODVS_BUCK_CTRL, 0, 0x8);
  137. dm_i2c_clrsetbits(dev, BD718XX_2ND_NODVS_BUCK_CTRL, 0, 0x8);
  138. dm_i2c_clrsetbits(dev, BD718XX_3RD_NODVS_BUCK_CTRL, 0, 0x8);
  139. dm_i2c_clrsetbits(dev, BD718XX_4TH_NODVS_BUCK_CTRL, 0, 0x8);
  140. /* increase VDD_0P95 (VDD_GPU/VPU/DRAM) to 0.975v for 1.5Ghz DDR */
  141. dm_i2c_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
  142. /* increase VDD_SOC to 0.85v before first DRAM access */
  143. dm_i2c_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
  144. /* increase VDD_ARM to 0.92v for 800 and 1600Mhz */
  145. dm_i2c_reg_write(dev, BD718XX_BUCK2_VOLT_RUN, 0x16);
  146. /* Lock the PMIC regs */
  147. dm_i2c_reg_write(dev, BD718XX_REGLOCK, 0x11);
  148. }
  149. return 0;
  150. }
  151. void board_init_f(ulong dummy)
  152. {
  153. struct udevice *dev;
  154. int ret;
  155. int dram_sz;
  156. arch_cpu_init();
  157. init_uart_clk(1);
  158. board_early_init_f();
  159. timer_init();
  160. preloader_console_init();
  161. /* Clear the BSS. */
  162. memset(__bss_start, 0, __bss_end - __bss_start);
  163. ret = spl_early_init();
  164. if (ret) {
  165. debug("spl_early_init() failed: %d\n", ret);
  166. hang();
  167. }
  168. ret = uclass_get_device_by_name(UCLASS_CLK,
  169. "clock-controller@30380000",
  170. &dev);
  171. if (ret < 0) {
  172. printf("Failed to find clock node. Check device tree\n");
  173. hang();
  174. }
  175. enable_tzc380();
  176. /* need to hold PCIe switch in reset otherwise it can lock i2c bus EEPROM is on */
  177. gpio_request(PCIE_RSTN, "perst#");
  178. gpio_direction_output(PCIE_RSTN, 0);
  179. /* GSC */
  180. dram_sz = gsc_init(0);
  181. /* PMIC */
  182. power_init_board();
  183. /* DDR initialization */
  184. spl_dram_init(dram_sz);
  185. board_init_r(NULL, 0);
  186. }
  187. /* determine prioritized order of boot devices to load U-Boot from */
  188. void board_boot_order(u32 *spl_boot_list)
  189. {
  190. /*
  191. * If the SPL was loaded via serial loader, we try to get
  192. * U-Boot proper via USB SDP.
  193. */
  194. if (spl_boot_device() == BOOT_DEVICE_BOARD)
  195. spl_boot_list[0] = BOOT_DEVICE_BOARD;
  196. /* we have only eMMC in default venice dt */
  197. spl_boot_list[0] = BOOT_DEVICE_MMC1;
  198. }
  199. /* return boot device based on where the SPL was loaded from */
  200. int spl_board_boot_device(enum boot_device boot_dev_spl)
  201. {
  202. switch (boot_dev_spl) {
  203. case USB_BOOT:
  204. return BOOT_DEVICE_BOARD;
  205. /* SDHC2 */
  206. case SD2_BOOT:
  207. case MMC2_BOOT:
  208. return BOOT_DEVICE_MMC1;
  209. /* SDHC3 */
  210. case SD3_BOOT:
  211. case MMC3_BOOT:
  212. return BOOT_DEVICE_MMC2;
  213. default:
  214. return BOOT_DEVICE_NONE;
  215. }
  216. }