gw_ventana_spl.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Gateworks Corporation
  4. * Author: Tim Harvey <tharvey@gateworks.com>
  5. */
  6. #include <common.h>
  7. #include <env.h>
  8. #include <hang.h>
  9. #include <init.h>
  10. #include <log.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/crm_regs.h>
  13. #include <asm/arch/mx6-ddr.h>
  14. #include <asm/arch/mx6-pins.h>
  15. #include <asm/arch/sys_proto.h>
  16. #include <asm/mach-imx/boot_mode.h>
  17. #include <asm/mach-imx/iomux-v3.h>
  18. #include <asm/mach-imx/mxc_i2c.h>
  19. #include <env.h>
  20. #include <i2c.h>
  21. #include <spl.h>
  22. #include "gsc.h"
  23. #include "common.h"
  24. #define RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
  25. #define GSC_EEPROM_DDR_SIZE 0x2B /* enum (512,1024,2048) MB */
  26. #define GSC_EEPROM_DDR_WIDTH 0x2D /* enum (32,64) bit */
  27. /* configure MX6Q/DUAL mmdc DDR io registers */
  28. struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
  29. /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
  30. .dram_sdclk_0 = 0x00020030,
  31. .dram_sdclk_1 = 0x00020030,
  32. .dram_cas = 0x00020030,
  33. .dram_ras = 0x00020030,
  34. .dram_reset = 0x00020030,
  35. /* SDCKE[0:1]: 100k pull-up */
  36. .dram_sdcke0 = 0x00003000,
  37. .dram_sdcke1 = 0x00003000,
  38. /* SDBA2: pull-up disabled */
  39. .dram_sdba2 = 0x00000000,
  40. /* SDODT[0:1]: 100k pull-up, 40 ohm */
  41. .dram_sdodt0 = 0x00003030,
  42. .dram_sdodt1 = 0x00003030,
  43. /* SDQS[0:7]: Differential input, 40 ohm */
  44. .dram_sdqs0 = 0x00000030,
  45. .dram_sdqs1 = 0x00000030,
  46. .dram_sdqs2 = 0x00000030,
  47. .dram_sdqs3 = 0x00000030,
  48. .dram_sdqs4 = 0x00000030,
  49. .dram_sdqs5 = 0x00000030,
  50. .dram_sdqs6 = 0x00000030,
  51. .dram_sdqs7 = 0x00000030,
  52. /* DQM[0:7]: Differential input, 40 ohm */
  53. .dram_dqm0 = 0x00020030,
  54. .dram_dqm1 = 0x00020030,
  55. .dram_dqm2 = 0x00020030,
  56. .dram_dqm3 = 0x00020030,
  57. .dram_dqm4 = 0x00020030,
  58. .dram_dqm5 = 0x00020030,
  59. .dram_dqm6 = 0x00020030,
  60. .dram_dqm7 = 0x00020030,
  61. };
  62. /* configure MX6Q/DUAL mmdc GRP io registers */
  63. struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
  64. /* DDR3 */
  65. .grp_ddr_type = 0x000c0000,
  66. .grp_ddrmode_ctl = 0x00020000,
  67. /* disable DDR pullups */
  68. .grp_ddrpke = 0x00000000,
  69. /* ADDR[00:16], SDBA[0:1]: 40 ohm */
  70. .grp_addds = 0x00000030,
  71. /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
  72. .grp_ctlds = 0x00000030,
  73. /* DATA[00:63]: Differential input, 40 ohm */
  74. .grp_ddrmode = 0x00020000,
  75. .grp_b0ds = 0x00000030,
  76. .grp_b1ds = 0x00000030,
  77. .grp_b2ds = 0x00000030,
  78. .grp_b3ds = 0x00000030,
  79. .grp_b4ds = 0x00000030,
  80. .grp_b5ds = 0x00000030,
  81. .grp_b6ds = 0x00000030,
  82. .grp_b7ds = 0x00000030,
  83. };
  84. /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
  85. struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
  86. /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
  87. .dram_sdclk_0 = 0x00020030,
  88. .dram_sdclk_1 = 0x00020030,
  89. .dram_cas = 0x00020030,
  90. .dram_ras = 0x00020030,
  91. .dram_reset = 0x00020030,
  92. /* SDCKE[0:1]: 100k pull-up */
  93. .dram_sdcke0 = 0x00003000,
  94. .dram_sdcke1 = 0x00003000,
  95. /* SDBA2: pull-up disabled */
  96. .dram_sdba2 = 0x00000000,
  97. /* SDODT[0:1]: 100k pull-up, 40 ohm */
  98. .dram_sdodt0 = 0x00003030,
  99. .dram_sdodt1 = 0x00003030,
  100. /* SDQS[0:7]: Differential input, 40 ohm */
  101. .dram_sdqs0 = 0x00000030,
  102. .dram_sdqs1 = 0x00000030,
  103. .dram_sdqs2 = 0x00000030,
  104. .dram_sdqs3 = 0x00000030,
  105. .dram_sdqs4 = 0x00000030,
  106. .dram_sdqs5 = 0x00000030,
  107. .dram_sdqs6 = 0x00000030,
  108. .dram_sdqs7 = 0x00000030,
  109. /* DQM[0:7]: Differential input, 40 ohm */
  110. .dram_dqm0 = 0x00020030,
  111. .dram_dqm1 = 0x00020030,
  112. .dram_dqm2 = 0x00020030,
  113. .dram_dqm3 = 0x00020030,
  114. .dram_dqm4 = 0x00020030,
  115. .dram_dqm5 = 0x00020030,
  116. .dram_dqm6 = 0x00020030,
  117. .dram_dqm7 = 0x00020030,
  118. };
  119. /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
  120. struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
  121. /* DDR3 */
  122. .grp_ddr_type = 0x000c0000,
  123. /* SDQS[0:7]: Differential input, 40 ohm */
  124. .grp_ddrmode_ctl = 0x00020000,
  125. /* disable DDR pullups */
  126. .grp_ddrpke = 0x00000000,
  127. /* ADDR[00:16], SDBA[0:1]: 40 ohm */
  128. .grp_addds = 0x00000030,
  129. /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
  130. .grp_ctlds = 0x00000030,
  131. /* DATA[00:63]: Differential input, 40 ohm */
  132. .grp_ddrmode = 0x00020000,
  133. .grp_b0ds = 0x00000030,
  134. .grp_b1ds = 0x00000030,
  135. .grp_b2ds = 0x00000030,
  136. .grp_b3ds = 0x00000030,
  137. .grp_b4ds = 0x00000030,
  138. .grp_b5ds = 0x00000030,
  139. .grp_b6ds = 0x00000030,
  140. .grp_b7ds = 0x00000030,
  141. };
  142. /* MT41K64M16JT-125 (1Gb density) */
  143. static struct mx6_ddr3_cfg mt41k64m16jt_125 = {
  144. .mem_speed = 1600,
  145. .density = 1,
  146. .width = 16,
  147. .banks = 8,
  148. .rowaddr = 13,
  149. .coladdr = 10,
  150. .pagesz = 2,
  151. .trcd = 1375,
  152. .trcmin = 4875,
  153. .trasmin = 3500,
  154. };
  155. /* MT41K128M16JT-125 (2Gb density) */
  156. static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
  157. .mem_speed = 1600,
  158. .density = 2,
  159. .width = 16,
  160. .banks = 8,
  161. .rowaddr = 14,
  162. .coladdr = 10,
  163. .pagesz = 2,
  164. .trcd = 1375,
  165. .trcmin = 4875,
  166. .trasmin = 3500,
  167. };
  168. /* MT41K256M16HA-125 (4Gb density) */
  169. static struct mx6_ddr3_cfg mt41k256m16ha_125 = {
  170. .mem_speed = 1600,
  171. .density = 4,
  172. .width = 16,
  173. .banks = 8,
  174. .rowaddr = 15,
  175. .coladdr = 10,
  176. .pagesz = 2,
  177. .trcd = 1375,
  178. .trcmin = 4875,
  179. .trasmin = 3500,
  180. };
  181. /* MT41K512M16HA-125 (8Gb density) */
  182. static struct mx6_ddr3_cfg mt41k512m16ha_125 = {
  183. .mem_speed = 1600,
  184. .density = 8,
  185. .width = 16,
  186. .banks = 8,
  187. .rowaddr = 16,
  188. .coladdr = 10,
  189. .pagesz = 2,
  190. .trcd = 1375,
  191. .trcmin = 4875,
  192. .trasmin = 3500,
  193. };
  194. /*
  195. * calibration - these are the various CPU/DDR3 combinations we support
  196. */
  197. static struct mx6_mmdc_calibration mx6sdl_64x16_mmdc_calib = {
  198. /* write leveling calibration determine */
  199. .p0_mpwldectrl0 = 0x004C004E,
  200. .p0_mpwldectrl1 = 0x00440044,
  201. /* Read DQS Gating calibration */
  202. .p0_mpdgctrl0 = 0x42440247,
  203. .p0_mpdgctrl1 = 0x02310232,
  204. /* Read Calibration: DQS delay relative to DQ read access */
  205. .p0_mprddlctl = 0x45424746,
  206. /* Write Calibration: DQ/DM delay relative to DQS write access */
  207. .p0_mpwrdlctl = 0x33382C31,
  208. };
  209. /* TODO: update with calibrated values */
  210. static struct mx6_mmdc_calibration mx6dq_64x64_mmdc_calib = {
  211. /* write leveling calibration determine */
  212. .p0_mpwldectrl0 = 0x00190017,
  213. .p0_mpwldectrl1 = 0x00140026,
  214. .p1_mpwldectrl0 = 0x0021001C,
  215. .p1_mpwldectrl1 = 0x0011001D,
  216. /* Read DQS Gating calibration */
  217. .p0_mpdgctrl0 = 0x43380347,
  218. .p0_mpdgctrl1 = 0x433C034D,
  219. .p1_mpdgctrl0 = 0x032C0324,
  220. .p1_mpdgctrl1 = 0x03310232,
  221. /* Read Calibration: DQS delay relative to DQ read access */
  222. .p0_mprddlctl = 0x3C313539,
  223. .p1_mprddlctl = 0x37343141,
  224. /* Write Calibration: DQ/DM delay relative to DQS write access */
  225. .p0_mpwrdlctl = 0x36393C39,
  226. .p1_mpwrdlctl = 0x42344438,
  227. };
  228. /* TODO: update with calibrated values */
  229. static struct mx6_mmdc_calibration mx6sdl_64x64_mmdc_calib = {
  230. /* write leveling calibration determine */
  231. .p0_mpwldectrl0 = 0x003C003C,
  232. .p0_mpwldectrl1 = 0x001F002A,
  233. .p1_mpwldectrl0 = 0x00330038,
  234. .p1_mpwldectrl1 = 0x0022003F,
  235. /* Read DQS Gating calibration */
  236. .p0_mpdgctrl0 = 0x42410244,
  237. .p0_mpdgctrl1 = 0x4234023A,
  238. .p1_mpdgctrl0 = 0x022D022D,
  239. .p1_mpdgctrl1 = 0x021C0228,
  240. /* Read Calibration: DQS delay relative to DQ read access */
  241. .p0_mprddlctl = 0x484A4C4B,
  242. .p1_mprddlctl = 0x4B4D4E4B,
  243. /* Write Calibration: DQ/DM delay relative to DQS write access */
  244. .p0_mpwrdlctl = 0x33342B32,
  245. .p1_mpwrdlctl = 0x3933332B,
  246. };
  247. static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = {
  248. /* write leveling calibration determine */
  249. .p0_mpwldectrl0 = 0x001B0016,
  250. .p0_mpwldectrl1 = 0x000C000E,
  251. /* Read DQS Gating calibration */
  252. .p0_mpdgctrl0 = 0x4324033A,
  253. .p0_mpdgctrl1 = 0x00000000,
  254. /* Read Calibration: DQS delay relative to DQ read access */
  255. .p0_mprddlctl = 0x40403438,
  256. /* Write Calibration: DQ/DM delay relative to DQS write access */
  257. .p0_mpwrdlctl = 0x40403D36,
  258. };
  259. static struct mx6_mmdc_calibration mx6sdl_256x16_mmdc_calib = {
  260. /* write leveling calibration determine */
  261. .p0_mpwldectrl0 = 0x00420043,
  262. .p0_mpwldectrl1 = 0x0016001A,
  263. /* Read DQS Gating calibration */
  264. .p0_mpdgctrl0 = 0x4238023B,
  265. .p0_mpdgctrl1 = 0x00000000,
  266. /* Read Calibration: DQS delay relative to DQ read access */
  267. .p0_mprddlctl = 0x40404849,
  268. /* Write Calibration: DQ/DM delay relative to DQS write access */
  269. .p0_mpwrdlctl = 0x40402E2F,
  270. };
  271. static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib = {
  272. /* write leveling calibration determine */
  273. .p0_mpwldectrl0 = 0x00190017,
  274. .p0_mpwldectrl1 = 0x00140026,
  275. /* Read DQS Gating calibration */
  276. .p0_mpdgctrl0 = 0x43380347,
  277. .p0_mpdgctrl1 = 0x433C034D,
  278. /* Read Calibration: DQS delay relative to DQ read access */
  279. .p0_mprddlctl = 0x3C313539,
  280. /* Write Calibration: DQ/DM delay relative to DQS write access */
  281. .p0_mpwrdlctl = 0x36393C39,
  282. };
  283. static struct mx6_mmdc_calibration mx6sdl_128x32_mmdc_calib = {
  284. /* write leveling calibration determine */
  285. .p0_mpwldectrl0 = 0x003C003C,
  286. .p0_mpwldectrl1 = 0x001F002A,
  287. /* Read DQS Gating calibration */
  288. .p0_mpdgctrl0 = 0x42410244,
  289. .p0_mpdgctrl1 = 0x4234023A,
  290. /* Read Calibration: DQS delay relative to DQ read access */
  291. .p0_mprddlctl = 0x484A4C4B,
  292. /* Write Calibration: DQ/DM delay relative to DQS write access */
  293. .p0_mpwrdlctl = 0x33342B32,
  294. };
  295. static struct mx6_mmdc_calibration mx6dq_128x64_mmdc_calib = {
  296. /* write leveling calibration determine */
  297. .p0_mpwldectrl0 = 0x00190017,
  298. .p0_mpwldectrl1 = 0x00140026,
  299. .p1_mpwldectrl0 = 0x0021001C,
  300. .p1_mpwldectrl1 = 0x0011001D,
  301. /* Read DQS Gating calibration */
  302. .p0_mpdgctrl0 = 0x43380347,
  303. .p0_mpdgctrl1 = 0x433C034D,
  304. .p1_mpdgctrl0 = 0x032C0324,
  305. .p1_mpdgctrl1 = 0x03310232,
  306. /* Read Calibration: DQS delay relative to DQ read access */
  307. .p0_mprddlctl = 0x3C313539,
  308. .p1_mprddlctl = 0x37343141,
  309. /* Write Calibration: DQ/DM delay relative to DQS write access */
  310. .p0_mpwrdlctl = 0x36393C39,
  311. .p1_mpwrdlctl = 0x42344438,
  312. };
  313. static struct mx6_mmdc_calibration mx6sdl_128x64_mmdc_calib = {
  314. /* write leveling calibration determine */
  315. .p0_mpwldectrl0 = 0x003C003C,
  316. .p0_mpwldectrl1 = 0x001F002A,
  317. .p1_mpwldectrl0 = 0x00330038,
  318. .p1_mpwldectrl1 = 0x0022003F,
  319. /* Read DQS Gating calibration */
  320. .p0_mpdgctrl0 = 0x42410244,
  321. .p0_mpdgctrl1 = 0x4234023A,
  322. .p1_mpdgctrl0 = 0x022D022D,
  323. .p1_mpdgctrl1 = 0x021C0228,
  324. /* Read Calibration: DQS delay relative to DQ read access */
  325. .p0_mprddlctl = 0x484A4C4B,
  326. .p1_mprddlctl = 0x4B4D4E4B,
  327. /* Write Calibration: DQ/DM delay relative to DQS write access */
  328. .p0_mpwrdlctl = 0x33342B32,
  329. .p1_mpwrdlctl = 0x3933332B,
  330. };
  331. static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib = {
  332. /* write leveling calibration determine */
  333. .p0_mpwldectrl0 = 0x001E001A,
  334. .p0_mpwldectrl1 = 0x0026001F,
  335. /* Read DQS Gating calibration */
  336. .p0_mpdgctrl0 = 0x43370349,
  337. .p0_mpdgctrl1 = 0x032D0327,
  338. /* Read Calibration: DQS delay relative to DQ read access */
  339. .p0_mprddlctl = 0x3D303639,
  340. /* Write Calibration: DQ/DM delay relative to DQS write access */
  341. .p0_mpwrdlctl = 0x32363934,
  342. };
  343. static struct mx6_mmdc_calibration mx6sdl_256x32_mmdc_calib = {
  344. /* write leveling calibration determine */
  345. .p0_mpwldectrl0 = 0X00480047,
  346. .p0_mpwldectrl1 = 0X003D003F,
  347. /* Read DQS Gating calibration */
  348. .p0_mpdgctrl0 = 0X423E0241,
  349. .p0_mpdgctrl1 = 0X022B022C,
  350. /* Read Calibration: DQS delay relative to DQ read access */
  351. .p0_mprddlctl = 0X49454A4A,
  352. /* Write Calibration: DQ/DM delay relative to DQS write access */
  353. .p0_mpwrdlctl = 0X2E372C32,
  354. };
  355. static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = {
  356. /* write leveling calibration determine */
  357. .p0_mpwldectrl0 = 0X00220021,
  358. .p0_mpwldectrl1 = 0X00200030,
  359. .p1_mpwldectrl0 = 0X002D0027,
  360. .p1_mpwldectrl1 = 0X00150026,
  361. /* Read DQS Gating calibration */
  362. .p0_mpdgctrl0 = 0x43330342,
  363. .p0_mpdgctrl1 = 0x0339034A,
  364. .p1_mpdgctrl0 = 0x032F0325,
  365. .p1_mpdgctrl1 = 0x032F022E,
  366. /* Read Calibration: DQS delay relative to DQ read access */
  367. .p0_mprddlctl = 0X3A2E3437,
  368. .p1_mprddlctl = 0X35312F3F,
  369. /* Write Calibration: DQ/DM delay relative to DQS write access */
  370. .p0_mpwrdlctl = 0X33363B37,
  371. .p1_mpwrdlctl = 0X40304239,
  372. };
  373. static struct mx6_mmdc_calibration mx6sdl_256x64_mmdc_calib = {
  374. /* write leveling calibration determine */
  375. .p0_mpwldectrl0 = 0x0048004A,
  376. .p0_mpwldectrl1 = 0x003F004A,
  377. .p1_mpwldectrl0 = 0x001E0028,
  378. .p1_mpwldectrl1 = 0x002C0043,
  379. /* Read DQS Gating calibration */
  380. .p0_mpdgctrl0 = 0x02250219,
  381. .p0_mpdgctrl1 = 0x01790202,
  382. .p1_mpdgctrl0 = 0x02080208,
  383. .p1_mpdgctrl1 = 0x016C0175,
  384. /* Read Calibration: DQS delay relative to DQ read access */
  385. .p0_mprddlctl = 0x4A4C4D4C,
  386. .p1_mprddlctl = 0x494C4A48,
  387. /* Write Calibration: DQ/DM delay relative to DQS write access */
  388. .p0_mpwrdlctl = 0x403F3437,
  389. .p1_mpwrdlctl = 0x383A3930,
  390. };
  391. static struct mx6_mmdc_calibration mx6sdl_256x64x2_mmdc_calib = {
  392. /* write leveling calibration determine */
  393. .p0_mpwldectrl0 = 0x001F003F,
  394. .p0_mpwldectrl1 = 0x001F001F,
  395. .p1_mpwldectrl0 = 0x001F004E,
  396. .p1_mpwldectrl1 = 0x0059001F,
  397. /* Read DQS Gating calibration */
  398. .p0_mpdgctrl0 = 0x42220225,
  399. .p0_mpdgctrl1 = 0x0213021F,
  400. .p1_mpdgctrl0 = 0x022C0242,
  401. .p1_mpdgctrl1 = 0x022C0244,
  402. /* Read Calibration: DQS delay relative to DQ read access */
  403. .p0_mprddlctl = 0x474A4C4A,
  404. .p1_mprddlctl = 0x48494C45,
  405. /* Write Calibration: DQ/DM delay relative to DQS write access */
  406. .p0_mpwrdlctl = 0x3F3F3F36,
  407. .p1_mpwrdlctl = 0x3F36363F,
  408. };
  409. static struct mx6_mmdc_calibration mx6sdl_128x64x2_mmdc_calib = {
  410. /* write leveling calibration determine */
  411. .p0_mpwldectrl0 = 0x001F003F,
  412. .p0_mpwldectrl1 = 0x001F001F,
  413. .p1_mpwldectrl0 = 0x001F004E,
  414. .p1_mpwldectrl1 = 0x0059001F,
  415. /* Read DQS Gating calibration */
  416. .p0_mpdgctrl0 = 0x42220225,
  417. .p0_mpdgctrl1 = 0x0213021F,
  418. .p1_mpdgctrl0 = 0x022C0242,
  419. .p1_mpdgctrl1 = 0x022C0244,
  420. /* Read Calibration: DQS delay relative to DQ read access */
  421. .p0_mprddlctl = 0x474A4C4A,
  422. .p1_mprddlctl = 0x48494C45,
  423. /* Write Calibration: DQ/DM delay relative to DQS write access */
  424. .p0_mpwrdlctl = 0x3F3F3F36,
  425. .p1_mpwrdlctl = 0x3F36363F,
  426. };
  427. static struct mx6_mmdc_calibration mx6dq_512x32_mmdc_calib = {
  428. /* write leveling calibration determine */
  429. .p0_mpwldectrl0 = 0x002A0025,
  430. .p0_mpwldectrl1 = 0x003A002A,
  431. /* Read DQS Gating calibration */
  432. .p0_mpdgctrl0 = 0x43430356,
  433. .p0_mpdgctrl1 = 0x033C0335,
  434. /* Read Calibration: DQS delay relative to DQ read access */
  435. .p0_mprddlctl = 0x4B373F42,
  436. /* Write Calibration: DQ/DM delay relative to DQS write access */
  437. .p0_mpwrdlctl = 0x303E3C36,
  438. };
  439. static struct mx6_mmdc_calibration mx6dq_512x64_mmdc_calib = {
  440. /* write leveling calibration determine */
  441. .p0_mpwldectrl0 = 0x00230020,
  442. .p0_mpwldectrl1 = 0x002F002A,
  443. .p1_mpwldectrl0 = 0x001D0027,
  444. .p1_mpwldectrl1 = 0x00100023,
  445. /* Read DQS Gating calibration */
  446. .p0_mpdgctrl0 = 0x03250339,
  447. .p0_mpdgctrl1 = 0x031C0316,
  448. .p1_mpdgctrl0 = 0x03210331,
  449. .p1_mpdgctrl1 = 0x031C025A,
  450. /* Read Calibration: DQS delay relative to DQ read access */
  451. .p0_mprddlctl = 0x40373C40,
  452. .p1_mprddlctl = 0x3A373646,
  453. /* Write Calibration: DQ/DM delay relative to DQS write access */
  454. .p0_mpwrdlctl = 0x2E353933,
  455. .p1_mpwrdlctl = 0x3C2F3F35,
  456. };
  457. static void spl_dram_init(int width, int size_mb, int board_model)
  458. {
  459. struct mx6_ddr3_cfg *mem = NULL;
  460. struct mx6_mmdc_calibration *calib = NULL;
  461. struct mx6_ddr_sysinfo sysinfo = {
  462. /* width of data bus:0=16,1=32,2=64 */
  463. .dsize = width/32,
  464. /* config for full 4GB range so that get_mem_size() works */
  465. .cs_density = 32, /* 32Gb per CS */
  466. /* single chip select */
  467. .ncs = 1,
  468. .cs1_mirror = 0,
  469. .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
  470. #ifdef RTT_NOM_120OHM
  471. .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
  472. #else
  473. .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
  474. #endif
  475. .walat = 1, /* Write additional latency */
  476. .ralat = 5, /* Read additional latency */
  477. .mif3_mode = 3, /* Command prediction working mode */
  478. .bi_on = 1, /* Bank interleaving enabled */
  479. .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
  480. .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
  481. .pd_fast_exit = 1, /* enable precharge power-down fast exit */
  482. .ddr_type = DDR_TYPE_DDR3,
  483. .refsel = 1, /* Refresh cycles at 32KHz */
  484. .refr = 7, /* 8 refresh commands per refresh cycle */
  485. };
  486. /*
  487. * MMDC Calibration requires the following data:
  488. * mx6_mmdc_calibration - board-specific calibration (routing delays)
  489. * these calibration values depend on board routing, SoC, and DDR
  490. * mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
  491. * mx6_ddr_cfg - chip specific timing/layout details
  492. */
  493. if (width == 16 && size_mb == 128) {
  494. mem = &mt41k64m16jt_125;
  495. if (is_cpu_type(MXC_CPU_MX6Q))
  496. ;
  497. else
  498. calib = &mx6sdl_64x16_mmdc_calib;
  499. debug("1gB density\n");
  500. } else if (width == 16 && size_mb == 256) {
  501. /* 1x 2Gb density chip - same calib as 2x 2Gb */
  502. mem = &mt41k128m16jt_125;
  503. if (is_cpu_type(MXC_CPU_MX6Q))
  504. calib = &mx6dq_128x32_mmdc_calib;
  505. else
  506. calib = &mx6sdl_128x32_mmdc_calib;
  507. debug("2gB density\n");
  508. } else if (width == 16 && size_mb == 512) {
  509. mem = &mt41k256m16ha_125;
  510. if (is_cpu_type(MXC_CPU_MX6Q))
  511. calib = &mx6dq_256x16_mmdc_calib;
  512. else
  513. calib = &mx6sdl_256x16_mmdc_calib;
  514. debug("4gB density\n");
  515. } else if (width == 16 && size_mb == 1024) {
  516. mem = &mt41k512m16ha_125;
  517. if (is_cpu_type(MXC_CPU_MX6Q))
  518. calib = &mx6dq_512x32_mmdc_calib;
  519. debug("8gB density\n");
  520. } else if (width == 32 && size_mb == 256) {
  521. /* Same calib as width==16, size==128 */
  522. mem = &mt41k64m16jt_125;
  523. if (is_cpu_type(MXC_CPU_MX6Q))
  524. ;
  525. else
  526. calib = &mx6sdl_64x16_mmdc_calib;
  527. debug("1gB density\n");
  528. } else if (width == 32 && size_mb == 512) {
  529. mem = &mt41k128m16jt_125;
  530. if (is_cpu_type(MXC_CPU_MX6Q))
  531. calib = &mx6dq_128x32_mmdc_calib;
  532. else
  533. calib = &mx6sdl_128x32_mmdc_calib;
  534. debug("2gB density\n");
  535. } else if (width == 32 && size_mb == 1024) {
  536. mem = &mt41k256m16ha_125;
  537. if (is_cpu_type(MXC_CPU_MX6Q))
  538. calib = &mx6dq_256x32_mmdc_calib;
  539. else
  540. calib = &mx6sdl_256x32_mmdc_calib;
  541. debug("4gB density\n");
  542. } else if (width == 32 && size_mb == 2048) {
  543. mem = &mt41k512m16ha_125;
  544. if (is_cpu_type(MXC_CPU_MX6Q))
  545. calib = &mx6dq_512x32_mmdc_calib;
  546. debug("8gB density\n");
  547. } else if (width == 64 && size_mb == 512) {
  548. mem = &mt41k64m16jt_125;
  549. debug("1gB density\n");
  550. if (is_cpu_type(MXC_CPU_MX6Q))
  551. calib = &mx6dq_64x64_mmdc_calib;
  552. else
  553. calib = &mx6sdl_64x64_mmdc_calib;
  554. } else if (width == 64 && size_mb == 1024) {
  555. mem = &mt41k128m16jt_125;
  556. if (is_cpu_type(MXC_CPU_MX6Q))
  557. calib = &mx6dq_128x64_mmdc_calib;
  558. else
  559. calib = &mx6sdl_128x64_mmdc_calib;
  560. debug("2gB density\n");
  561. } else if (width == 64 && size_mb == 2048) {
  562. switch(board_model) {
  563. case GW5905:
  564. /* 8xMT41K128M16 (2GiB) fly-by mirrored 2-chipsels */
  565. mem = &mt41k128m16jt_125;
  566. debug("2gB density - 2 chipsel\n");
  567. if (!is_cpu_type(MXC_CPU_MX6Q)) {
  568. calib = &mx6sdl_128x64x2_mmdc_calib;
  569. sysinfo.ncs = 2;
  570. sysinfo.cs_density = 10; /* CS0_END=39 */
  571. sysinfo.cs1_mirror = 1; /* mirror enabled */
  572. }
  573. break;
  574. default:
  575. mem = &mt41k256m16ha_125;
  576. if (is_cpu_type(MXC_CPU_MX6Q))
  577. calib = &mx6dq_256x64_mmdc_calib;
  578. else
  579. calib = &mx6sdl_256x64_mmdc_calib;
  580. debug("4gB density\n");
  581. break;
  582. }
  583. } else if (width == 64 && size_mb == 4096) {
  584. switch(board_model) {
  585. case GW5903:
  586. /* 8xMT41K256M16 (4GiB) fly-by mirrored 2-chipsels */
  587. mem = &mt41k256m16ha_125;
  588. debug("4gB density - 2 chipsel\n");
  589. if (!is_cpu_type(MXC_CPU_MX6Q)) {
  590. calib = &mx6sdl_256x64x2_mmdc_calib;
  591. sysinfo.ncs = 2;
  592. sysinfo.cs_density = 18; /* CS0_END=71 */
  593. sysinfo.cs1_mirror = 1; /* mirror enabled */
  594. }
  595. break;
  596. default:
  597. mem = &mt41k512m16ha_125;
  598. if (is_cpu_type(MXC_CPU_MX6Q))
  599. calib = &mx6dq_512x64_mmdc_calib;
  600. debug("8gB density\n");
  601. break;
  602. }
  603. }
  604. if (!(mem && calib)) {
  605. puts("Error: Invalid Calibration/Board Configuration\n");
  606. printf("MEM : %s\n", mem ? "OKAY" : "NULL");
  607. printf("CALIB : %s\n", calib ? "OKAY" : "NULL");
  608. printf("CPUTYPE: %s\n",
  609. is_cpu_type(MXC_CPU_MX6Q) ? "IMX6Q" : "IMX6DL");
  610. printf("SIZE_MB: %d\n", size_mb);
  611. printf("WIDTH : %d\n", width);
  612. hang();
  613. }
  614. if (is_cpu_type(MXC_CPU_MX6Q))
  615. mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs,
  616. &mx6dq_grp_ioregs);
  617. else
  618. mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs,
  619. &mx6sdl_grp_ioregs);
  620. mx6_dram_cfg(&sysinfo, calib, mem);
  621. }
  622. static void ccgr_init(void)
  623. {
  624. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  625. writel(0x00C03F3F, &ccm->CCGR0);
  626. writel(0x0030FC03, &ccm->CCGR1);
  627. writel(0x0FFFC000, &ccm->CCGR2);
  628. writel(0x3FF00000, &ccm->CCGR3);
  629. writel(0xFFFFF300, &ccm->CCGR4); /* enable NAND/GPMI/BCH clks */
  630. writel(0x0F0000C3, &ccm->CCGR5);
  631. writel(0x000003FF, &ccm->CCGR6);
  632. }
  633. /*
  634. * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
  635. * - we have a stack and a place to store GD, both in SRAM
  636. * - no variable global data is available
  637. */
  638. void board_init_f(ulong dummy)
  639. {
  640. struct ventana_board_info ventana_info;
  641. int board_model;
  642. /* setup clock gating */
  643. ccgr_init();
  644. /* setup AIPS and disable watchdog */
  645. arch_cpu_init();
  646. /* setup AXI */
  647. gpr_init();
  648. /* iomux and setup of uart/i2c */
  649. setup_iomux_uart();
  650. setup_ventana_i2c(0);
  651. setup_ventana_i2c(1);
  652. /* setup GP timer */
  653. timer_init();
  654. /* UART clocks enabled and gd valid - init serial console */
  655. preloader_console_init();
  656. /* read/validate EEPROM info to determine board model and SDRAM cfg */
  657. board_model = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
  658. /* configure model-specific gpio */
  659. setup_iomux_gpio(board_model, &ventana_info);
  660. /* provide some some default: 32bit 128MB */
  661. if (GW_UNKNOWN == board_model)
  662. hang();
  663. /* configure MMDC for SDRAM width/size and per-model calibration */
  664. spl_dram_init(8 << ventana_info.sdram_width,
  665. 16 << ventana_info.sdram_size,
  666. board_model);
  667. }
  668. void board_boot_order(u32 *spl_boot_list)
  669. {
  670. spl_boot_list[0] = spl_boot_device();
  671. switch (spl_boot_list[0]) {
  672. case BOOT_DEVICE_NAND:
  673. spl_boot_list[1] = BOOT_DEVICE_MMC1;
  674. spl_boot_list[2] = BOOT_DEVICE_UART;
  675. break;
  676. case BOOT_DEVICE_MMC1:
  677. spl_boot_list[1] = BOOT_DEVICE_UART;
  678. break;
  679. }
  680. }
  681. /* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */
  682. /* its our chance to print info about boot device */
  683. static int board_type;
  684. void spl_board_init(void)
  685. {
  686. u32 boot_device;
  687. /* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 */
  688. boot_device = spl_boot_device();
  689. /* read eeprom again now that we have gd */
  690. board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
  691. if (board_type == GW_UNKNOWN)
  692. hang();
  693. switch (boot_device) {
  694. case BOOT_DEVICE_MMC1:
  695. puts("Booting from MMC\n");
  696. break;
  697. case BOOT_DEVICE_NAND:
  698. puts("Booting from NAND\n");
  699. break;
  700. case BOOT_DEVICE_SATA:
  701. puts("Booting from SATA\n");
  702. break;
  703. default:
  704. puts("Unknown boot device\n");
  705. }
  706. /* PMIC init */
  707. setup_pmic();
  708. }
  709. #ifdef CONFIG_SPL_OS_BOOT
  710. /* return 1 if we wish to boot to uboot vs os (falcon mode) */
  711. int spl_start_uboot(void)
  712. {
  713. unsigned char ret = 1;
  714. debug("%s\n", __func__);
  715. #ifdef CONFIG_SPL_ENV_SUPPORT
  716. env_init();
  717. env_load();
  718. debug("boot_os=%s\n", env_get("boot_os"));
  719. if (env_get_yesno("boot_os") == 1)
  720. ret = 0;
  721. #else
  722. /* use i2c-0:0x50:0x00 for falcon boot mode (0=linux, else uboot) */
  723. i2c_set_bus_num(0);
  724. gsc_i2c_read(0x50, 0x0, 1, &ret, 1);
  725. #endif
  726. if (!ret)
  727. gsc_boot_wd_disable();
  728. debug("%s booting %s\n", __func__, ret ? "uboot" : "linux");
  729. return ret;
  730. }
  731. #endif
  732. void spl_perform_fixups(struct spl_image_info *spl_image)
  733. {
  734. ft_early_fixup(spl_image->fdt_addr, board_type);
  735. }