gw_ventana.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2013 Gateworks Corporation
  4. *
  5. * Author: Tim Harvey <tharvey@gateworks.com>
  6. */
  7. #include <common.h>
  8. #include <asm/arch/clock.h>
  9. #include <asm/arch/crm_regs.h>
  10. #include <asm/arch/mx6-pins.h>
  11. #include <asm/arch/mxc_hdmi.h>
  12. #include <asm/arch/sys_proto.h>
  13. #include <asm/global_data.h>
  14. #include <asm/gpio.h>
  15. #include <asm/mach-imx/boot_mode.h>
  16. #include <asm/mach-imx/video.h>
  17. #include <asm/setup.h>
  18. #include <env.h>
  19. #include <hwconfig.h>
  20. #include <linux/ctype.h>
  21. #include <miiphy.h>
  22. #include <mtd_node.h>
  23. #include <linux/delay.h>
  24. #include <power/pmic.h>
  25. #include <fdt_support.h>
  26. #include <jffs2/load_kernel.h>
  27. #include "gsc.h"
  28. #include "common.h"
  29. DECLARE_GLOBAL_DATA_PTR;
  30. /*
  31. * EEPROM board info struct populated by read_eeprom so that we only have to
  32. * read it once.
  33. */
  34. struct ventana_board_info ventana_info;
  35. static int board_type;
  36. #ifdef CONFIG_USB_EHCI_MX6
  37. /* toggle USB_HUB_RST# for boards that have it; it is not defined in dt */
  38. int board_ehci_hcd_init(int port)
  39. {
  40. int gpio;
  41. /* USB HUB is always on P1 */
  42. if (port == 0)
  43. return 0;
  44. /* Reset USB HUB */
  45. switch (board_type) {
  46. case GW53xx:
  47. case GW552x:
  48. case GW5906:
  49. gpio = (IMX_GPIO_NR(1, 9));
  50. break;
  51. case GW54proto:
  52. case GW54xx:
  53. gpio = (IMX_GPIO_NR(1, 16));
  54. break;
  55. default:
  56. return 0;
  57. }
  58. /* request and toggle hub rst */
  59. gpio_request(gpio, "usb_hub_rst#");
  60. gpio_direction_output(gpio, 0);
  61. mdelay(2);
  62. gpio_set_value(gpio, 1);
  63. return 0;
  64. }
  65. #endif /* CONFIG_USB_EHCI_MX6 */
  66. /* configure eth0 PHY board-specific LED behavior */
  67. int board_phy_config(struct phy_device *phydev)
  68. {
  69. unsigned short val;
  70. /* Marvel 88E1510 */
  71. if (phydev->phy_id == 0x1410dd1) {
  72. puts("MV88E1510");
  73. /*
  74. * Page 3, Register 16: LED[2:0] Function Control Register
  75. * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
  76. * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
  77. */
  78. phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
  79. val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
  80. val &= 0xff00;
  81. val |= 0x0017;
  82. phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
  83. phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
  84. }
  85. /* TI DP83867 */
  86. else if (phydev->phy_id == 0x2000a231) {
  87. puts("TIDP83867 ");
  88. /* LED configuration */
  89. val = 0;
  90. val |= 0x5 << 4; /* LED1(Amber;Speed) : 1000BT link */
  91. val |= 0xb << 8; /* LED2(Green;Link/Act): blink for TX/RX act */
  92. phy_write(phydev, MDIO_DEVAD_NONE, 24, val);
  93. /* configure register 0x170 for ref CLKOUT */
  94. phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x001f);
  95. phy_write(phydev, MDIO_DEVAD_NONE, 14, 0x0170);
  96. phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x401f);
  97. val = phy_read(phydev, MDIO_DEVAD_NONE, 14);
  98. val &= ~0x1f00;
  99. val |= 0x0b00; /* chD tx clock*/
  100. phy_write(phydev, MDIO_DEVAD_NONE, 14, val);
  101. }
  102. if (phydev->drv->config)
  103. phydev->drv->config(phydev);
  104. return 0;
  105. }
  106. #ifdef CONFIG_MV88E61XX_SWITCH
  107. int mv88e61xx_hw_reset(struct phy_device *phydev)
  108. {
  109. struct mii_dev *bus = phydev->bus;
  110. /* GPIO[0] output, CLK125 */
  111. debug("enabling RGMII_REFCLK\n");
  112. bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
  113. 0x1a /*MV_SCRATCH_MISC*/,
  114. (1 << 15) | (0x62 /*MV_GPIO_DIR*/ << 8) | 0xfe);
  115. bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
  116. 0x1a /*MV_SCRATCH_MISC*/,
  117. (1 << 15) | (0x68 /*MV_GPIO01_CNTL*/ << 8) | 7);
  118. /* RGMII delay - Physical Control register bit[15:14] */
  119. debug("setting port%d RGMII rx/tx delay\n", CONFIG_MV88E61XX_CPU_PORT);
  120. /* forced 1000mbps full-duplex link */
  121. bus->write(bus, 0x10 + CONFIG_MV88E61XX_CPU_PORT, 0, 1, 0xc0fe);
  122. phydev->autoneg = AUTONEG_DISABLE;
  123. phydev->speed = SPEED_1000;
  124. phydev->duplex = DUPLEX_FULL;
  125. /* LED configuration: 7:4-green (8=Activity) 3:0 amber (8=Link) */
  126. bus->write(bus, 0x10, 0, 0x16, 0x8088);
  127. bus->write(bus, 0x11, 0, 0x16, 0x8088);
  128. bus->write(bus, 0x12, 0, 0x16, 0x8088);
  129. bus->write(bus, 0x13, 0, 0x16, 0x8088);
  130. return 0;
  131. }
  132. #endif // CONFIG_MV88E61XX_SWITCH
  133. #if defined(CONFIG_VIDEO_IPUV3)
  134. static void enable_hdmi(struct display_info_t const *dev)
  135. {
  136. imx_enable_hdmi_phy();
  137. }
  138. static int detect_i2c(struct display_info_t const *dev)
  139. {
  140. return i2c_set_bus_num(dev->bus) == 0 &&
  141. i2c_probe(dev->addr) == 0;
  142. }
  143. static void enable_lvds(struct display_info_t const *dev)
  144. {
  145. struct iomuxc *iomux = (struct iomuxc *)
  146. IOMUXC_BASE_ADDR;
  147. /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
  148. u32 reg = readl(&iomux->gpr[2]);
  149. reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
  150. writel(reg, &iomux->gpr[2]);
  151. /* Enable Backlight */
  152. gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
  153. gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
  154. gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
  155. SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
  156. gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
  157. }
  158. struct display_info_t const displays[] = {{
  159. /* HDMI Output */
  160. .bus = -1,
  161. .addr = 0,
  162. .pixfmt = IPU_PIX_FMT_RGB24,
  163. .detect = detect_hdmi,
  164. .enable = enable_hdmi,
  165. .mode = {
  166. .name = "HDMI",
  167. .refresh = 60,
  168. .xres = 1024,
  169. .yres = 768,
  170. .pixclock = 15385,
  171. .left_margin = 220,
  172. .right_margin = 40,
  173. .upper_margin = 21,
  174. .lower_margin = 7,
  175. .hsync_len = 60,
  176. .vsync_len = 10,
  177. .sync = FB_SYNC_EXT,
  178. .vmode = FB_VMODE_NONINTERLACED
  179. } }, {
  180. /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
  181. .bus = 2,
  182. .addr = 0x4,
  183. .pixfmt = IPU_PIX_FMT_LVDS666,
  184. .detect = detect_i2c,
  185. .enable = enable_lvds,
  186. .mode = {
  187. .name = "Hannstar-XGA",
  188. .refresh = 60,
  189. .xres = 1024,
  190. .yres = 768,
  191. .pixclock = 15385,
  192. .left_margin = 220,
  193. .right_margin = 40,
  194. .upper_margin = 21,
  195. .lower_margin = 7,
  196. .hsync_len = 60,
  197. .vsync_len = 10,
  198. .sync = FB_SYNC_EXT,
  199. .vmode = FB_VMODE_NONINTERLACED
  200. } }, {
  201. /* DLC700JMG-T-4 */
  202. .bus = 2,
  203. .addr = 0x38,
  204. .detect = NULL,
  205. .enable = enable_lvds,
  206. .pixfmt = IPU_PIX_FMT_LVDS666,
  207. .mode = {
  208. .name = "DLC700JMGT4",
  209. .refresh = 60,
  210. .xres = 1024, /* 1024x600active pixels */
  211. .yres = 600,
  212. .pixclock = 15385, /* 64MHz */
  213. .left_margin = 220,
  214. .right_margin = 40,
  215. .upper_margin = 21,
  216. .lower_margin = 7,
  217. .hsync_len = 60,
  218. .vsync_len = 10,
  219. .sync = FB_SYNC_EXT,
  220. .vmode = FB_VMODE_NONINTERLACED
  221. } }, {
  222. /* DLC0700XDP21LF-C-1 */
  223. .bus = 0,
  224. .addr = 0,
  225. .detect = NULL,
  226. .enable = enable_lvds,
  227. .pixfmt = IPU_PIX_FMT_LVDS666,
  228. .mode = {
  229. .name = "DLC0700XDP21LF",
  230. .refresh = 60,
  231. .xres = 1024, /* 1024x600active pixels */
  232. .yres = 600,
  233. .pixclock = 15385, /* 64MHz */
  234. .left_margin = 220,
  235. .right_margin = 40,
  236. .upper_margin = 21,
  237. .lower_margin = 7,
  238. .hsync_len = 60,
  239. .vsync_len = 10,
  240. .sync = FB_SYNC_EXT,
  241. .vmode = FB_VMODE_NONINTERLACED
  242. } }, {
  243. /* DLC800FIG-T-3 */
  244. .bus = 2,
  245. .addr = 0x14,
  246. .detect = NULL,
  247. .enable = enable_lvds,
  248. .pixfmt = IPU_PIX_FMT_LVDS666,
  249. .mode = {
  250. .name = "DLC800FIGT3",
  251. .refresh = 60,
  252. .xres = 1024, /* 1024x768 active pixels */
  253. .yres = 768,
  254. .pixclock = 15385, /* 64MHz */
  255. .left_margin = 220,
  256. .right_margin = 40,
  257. .upper_margin = 21,
  258. .lower_margin = 7,
  259. .hsync_len = 60,
  260. .vsync_len = 10,
  261. .sync = FB_SYNC_EXT,
  262. .vmode = FB_VMODE_NONINTERLACED
  263. } }, {
  264. .bus = 2,
  265. .addr = 0x5d,
  266. .detect = detect_i2c,
  267. .enable = enable_lvds,
  268. .pixfmt = IPU_PIX_FMT_LVDS666,
  269. .mode = {
  270. .name = "Z101WX01",
  271. .refresh = 60,
  272. .xres = 1280,
  273. .yres = 800,
  274. .pixclock = 15385, /* 64MHz */
  275. .left_margin = 220,
  276. .right_margin = 40,
  277. .upper_margin = 21,
  278. .lower_margin = 7,
  279. .hsync_len = 60,
  280. .vsync_len = 10,
  281. .sync = FB_SYNC_EXT,
  282. .vmode = FB_VMODE_NONINTERLACED
  283. }
  284. },
  285. };
  286. size_t display_count = ARRAY_SIZE(displays);
  287. static void setup_display(void)
  288. {
  289. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  290. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  291. int reg;
  292. enable_ipu_clock();
  293. imx_setup_hdmi();
  294. /* Turn on LDB0,IPU,IPU DI0 clocks */
  295. reg = __raw_readl(&mxc_ccm->CCGR3);
  296. reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
  297. writel(reg, &mxc_ccm->CCGR3);
  298. /* set LDB0, LDB1 clk select to 011/011 */
  299. reg = readl(&mxc_ccm->cs2cdr);
  300. reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
  301. |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
  302. reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
  303. |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
  304. writel(reg, &mxc_ccm->cs2cdr);
  305. reg = readl(&mxc_ccm->cscmr2);
  306. reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
  307. writel(reg, &mxc_ccm->cscmr2);
  308. reg = readl(&mxc_ccm->chsccdr);
  309. reg |= (CHSCCDR_CLK_SEL_LDB_DI0
  310. <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  311. writel(reg, &mxc_ccm->chsccdr);
  312. reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
  313. |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
  314. |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
  315. |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
  316. |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
  317. |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
  318. |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
  319. |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
  320. |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
  321. writel(reg, &iomux->gpr[2]);
  322. reg = readl(&iomux->gpr[3]);
  323. reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
  324. | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
  325. <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
  326. writel(reg, &iomux->gpr[3]);
  327. /* LVDS Backlight GPIO on LVDS connector - output low */
  328. SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
  329. gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
  330. }
  331. #endif /* CONFIG_VIDEO_IPUV3 */
  332. /* setup board specific PMIC */
  333. int power_init_board(void)
  334. {
  335. setup_pmic();
  336. return 0;
  337. }
  338. /*
  339. * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
  340. * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
  341. * properly and assert reset for 100ms.
  342. */
  343. #define MAX_PCI_DEVS 32
  344. struct pci_dev {
  345. pci_dev_t devfn;
  346. struct udevice *dev;
  347. unsigned short vendor;
  348. unsigned short device;
  349. unsigned short class;
  350. unsigned short busno; /* subbordinate busno */
  351. struct pci_dev *ppar;
  352. };
  353. struct pci_dev pci_devs[MAX_PCI_DEVS];
  354. int pci_devno;
  355. int pci_bridgeno;
  356. void board_pci_fixup_dev(struct udevice *bus, struct udevice *udev)
  357. {
  358. struct pci_child_plat *pdata = dev_get_parent_plat(udev);
  359. struct pci_dev *pdev = &pci_devs[pci_devno++];
  360. unsigned short vendor = pdata->vendor;
  361. unsigned short device = pdata->device;
  362. unsigned int class = pdata->class;
  363. pci_dev_t dev = dm_pci_get_bdf(udev);
  364. int i;
  365. debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
  366. PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
  367. /* store array of devs for later use in device-tree fixup */
  368. pdev->dev = udev;
  369. pdev->devfn = dev;
  370. pdev->vendor = vendor;
  371. pdev->device = device;
  372. pdev->class = class;
  373. pdev->ppar = NULL;
  374. if (class == PCI_CLASS_BRIDGE_PCI)
  375. pdev->busno = ++pci_bridgeno;
  376. else
  377. pdev->busno = 0;
  378. /* fixup RC - it should be 00:00.0 not 00:01.0 */
  379. if (PCI_BUS(dev) == 0)
  380. pdev->devfn = 0;
  381. /* find dev's parent */
  382. for (i = 0; i < pci_devno; i++) {
  383. if (pci_devs[i].busno == PCI_BUS(pdev->devfn)) {
  384. pdev->ppar = &pci_devs[i];
  385. break;
  386. }
  387. }
  388. /* assert downstream PERST# */
  389. if (vendor == PCI_VENDOR_ID_PLX &&
  390. (device & 0xfff0) == 0x8600 &&
  391. PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
  392. ulong val;
  393. debug("configuring PLX 860X downstream PERST#\n");
  394. pci_bus_read_config(bus, dev, 0x62c, &val, PCI_SIZE_32);
  395. val |= 0xaaa8; /* GPIO1-7 outputs */
  396. pci_bus_write_config(bus, dev, 0x62c, val, PCI_SIZE_32);
  397. pci_bus_read_config(bus, dev, 0x644, &val, PCI_SIZE_32);
  398. val |= 0xfe; /* GPIO1-7 output high */
  399. pci_bus_write_config(bus, dev, 0x644, val, PCI_SIZE_32);
  400. mdelay(100);
  401. }
  402. }
  403. #ifdef CONFIG_SERIAL_TAG
  404. /*
  405. * called when setting up ATAGS before booting kernel
  406. * populate serialnum from the following (in order of priority):
  407. * serial# env var
  408. * eeprom
  409. */
  410. void get_board_serial(struct tag_serialnr *serialnr)
  411. {
  412. char *serial = env_get("serial#");
  413. if (serial) {
  414. serialnr->high = 0;
  415. serialnr->low = dectoul(serial, NULL);
  416. } else if (ventana_info.model[0]) {
  417. serialnr->high = 0;
  418. serialnr->low = ventana_info.serial;
  419. } else {
  420. serialnr->high = 0;
  421. serialnr->low = 0;
  422. }
  423. }
  424. #endif
  425. /*
  426. * Board Support
  427. */
  428. int board_early_init_f(void)
  429. {
  430. #if defined(CONFIG_VIDEO_IPUV3)
  431. setup_display();
  432. #endif
  433. return 0;
  434. }
  435. int dram_init(void)
  436. {
  437. gd->ram_size = imx_ddr_size();
  438. return 0;
  439. }
  440. int board_init(void)
  441. {
  442. struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  443. clrsetbits_le32(&iomuxc_regs->gpr[1],
  444. IOMUXC_GPR1_OTG_ID_MASK,
  445. IOMUXC_GPR1_OTG_ID_GPIO1);
  446. /* address of linux boot parameters */
  447. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  448. /* read Gateworks EEPROM into global struct (used later) */
  449. setup_ventana_i2c(0);
  450. board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
  451. setup_ventana_i2c(1);
  452. setup_ventana_i2c(2);
  453. setup_iomux_gpio(board_type, &ventana_info);
  454. return 0;
  455. }
  456. int board_fit_config_name_match(const char *name)
  457. {
  458. static char init;
  459. const char *dtb;
  460. char buf[32];
  461. int i = 0;
  462. do {
  463. dtb = gsc_get_dtb_name(i++, buf, sizeof(buf));
  464. if (dtb && !strcmp(dtb, name)) {
  465. if (!init++)
  466. printf("DTB: %s\n", name);
  467. return 0;
  468. }
  469. } while (dtb);
  470. return -1;
  471. }
  472. #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
  473. /*
  474. * called during late init (after relocation and after board_init())
  475. * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
  476. * EEPROM read.
  477. */
  478. int checkboard(void)
  479. {
  480. struct ventana_board_info *info = &ventana_info;
  481. unsigned char buf[4];
  482. const char *p;
  483. int quiet; /* Quiet or minimal output mode */
  484. quiet = 0;
  485. p = env_get("quiet");
  486. if (p)
  487. quiet = simple_strtol(p, NULL, 10);
  488. else
  489. env_set("quiet", "0");
  490. puts("\nGateworks Corporation Copyright 2014\n");
  491. if (info->model[0]) {
  492. printf("Model: %s\n", info->model);
  493. printf("MFGDate: %02x-%02x-%02x%02x\n",
  494. info->mfgdate[0], info->mfgdate[1],
  495. info->mfgdate[2], info->mfgdate[3]);
  496. printf("Serial:%d\n", info->serial);
  497. } else {
  498. puts("Invalid EEPROM - board will not function fully\n");
  499. }
  500. if (quiet)
  501. return 0;
  502. /* Display GSC firmware revision/CRC/status */
  503. gsc_info(0);
  504. /* Display RTC */
  505. if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
  506. printf("RTC: %d\n",
  507. buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
  508. }
  509. return 0;
  510. }
  511. #endif
  512. #ifdef CONFIG_CMD_BMODE
  513. /*
  514. * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
  515. * see Table 8-11 and Table 5-9
  516. * BOOT_CFG1[7] = 1 (boot from NAND)
  517. * BOOT_CFG1[5] = 0 - raw NAND
  518. * BOOT_CFG1[4] = 0 - default pad settings
  519. * BOOT_CFG1[3:2] = 00 - devices = 1
  520. * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
  521. * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
  522. * BOOT_CFG2[2:1] = 01 - Pages In Block = 64
  523. * BOOT_CFG2[0] = 0 - Reset time 12ms
  524. */
  525. static const struct boot_mode board_boot_modes[] = {
  526. /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
  527. { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
  528. { "emmc2", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00) }, /* GW5600 */
  529. { "emmc3", MAKE_CFGVAL(0x60, 0x50, 0x00, 0x00) }, /* GW5903/4/5 */
  530. { NULL, 0 },
  531. };
  532. #endif
  533. /* late init */
  534. int misc_init_r(void)
  535. {
  536. struct ventana_board_info *info = &ventana_info;
  537. char buf[256];
  538. int i;
  539. /* set env vars based on EEPROM data */
  540. if (ventana_info.model[0]) {
  541. char str[16], fdt[36];
  542. char *p;
  543. const char *cputype = "";
  544. /*
  545. * FDT name will be prefixed with CPU type. Three versions
  546. * will be created each increasingly generic and bootloader
  547. * env scripts will try loading each from most specific to
  548. * least.
  549. */
  550. if (is_cpu_type(MXC_CPU_MX6Q) ||
  551. is_cpu_type(MXC_CPU_MX6D))
  552. cputype = "imx6q";
  553. else if (is_cpu_type(MXC_CPU_MX6DL) ||
  554. is_cpu_type(MXC_CPU_MX6SOLO))
  555. cputype = "imx6dl";
  556. env_set("soctype", cputype);
  557. if (8 << (ventana_info.nand_flash_size-1) >= 2048)
  558. env_set("flash_layout", "large");
  559. else
  560. env_set("flash_layout", "normal");
  561. memset(str, 0, sizeof(str));
  562. for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
  563. str[i] = tolower(info->model[i]);
  564. env_set("model", str);
  565. if (!env_get("fdt_file")) {
  566. sprintf(fdt, "%s-%s.dtb", cputype, str);
  567. env_set("fdt_file", fdt);
  568. }
  569. p = strchr(str, '-');
  570. if (p) {
  571. *p++ = 0;
  572. env_set("model_base", str);
  573. sprintf(fdt, "%s-%s.dtb", cputype, str);
  574. env_set("fdt_file1", fdt);
  575. if (board_type != GW551x &&
  576. board_type != GW552x &&
  577. board_type != GW553x &&
  578. board_type != GW560x)
  579. str[4] = 'x';
  580. str[5] = 'x';
  581. str[6] = 0;
  582. sprintf(fdt, "%s-%s.dtb", cputype, str);
  583. env_set("fdt_file2", fdt);
  584. }
  585. /* initialize env from EEPROM */
  586. if (test_bit(EECONFIG_ETH0, info->config) &&
  587. !env_get("ethaddr")) {
  588. eth_env_set_enetaddr("ethaddr", info->mac0);
  589. }
  590. if (test_bit(EECONFIG_ETH1, info->config) &&
  591. !env_get("eth1addr")) {
  592. eth_env_set_enetaddr("eth1addr", info->mac1);
  593. }
  594. /* board serial-number */
  595. sprintf(str, "%6d", info->serial);
  596. env_set("serial#", str);
  597. /* memory MB */
  598. sprintf(str, "%d", (int) (gd->ram_size >> 20));
  599. env_set("mem_mb", str);
  600. }
  601. /* Set a non-initialized hwconfig based on board configuration */
  602. if (!strcmp(env_get("hwconfig"), "_UNKNOWN_")) {
  603. buf[0] = 0;
  604. if (gpio_cfg[board_type].rs232_en)
  605. strcat(buf, "rs232;");
  606. for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
  607. char buf1[32];
  608. sprintf(buf1, "dio%d:mode=gpio;", i);
  609. if (strlen(buf) + strlen(buf1) < sizeof(buf))
  610. strcat(buf, buf1);
  611. }
  612. env_set("hwconfig", buf);
  613. }
  614. /* setup baseboard specific GPIO based on board and env */
  615. setup_board_gpio(board_type, info);
  616. #ifdef CONFIG_CMD_BMODE
  617. add_board_boot_modes(board_boot_modes);
  618. #endif
  619. /* disable boot watchdog */
  620. gsc_boot_wd_disable();
  621. return 0;
  622. }
  623. #ifdef CONFIG_OF_BOARD_SETUP
  624. static int ft_sethdmiinfmt(void *blob, char *mode)
  625. {
  626. int off;
  627. if (!mode)
  628. return -EINVAL;
  629. off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x");
  630. if (off < 0)
  631. return off;
  632. if (0 == strcasecmp(mode, "yuv422bt656")) {
  633. u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00,
  634. 0x00, 0x00, 0x00 };
  635. mode = "422_ccir";
  636. fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
  637. fdt_setprop_u32(blob, off, "vidout_trc", 1);
  638. fdt_setprop_u32(blob, off, "vidout_blc", 1);
  639. fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
  640. printf(" set HDMI input mode to %s\n", mode);
  641. } else if (0 == strcasecmp(mode, "yuv422smp")) {
  642. u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00,
  643. 0x82, 0x81, 0x00 };
  644. mode = "422_smp";
  645. fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
  646. fdt_setprop_u32(blob, off, "vidout_trc", 0);
  647. fdt_setprop_u32(blob, off, "vidout_blc", 0);
  648. fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
  649. printf(" set HDMI input mode to %s\n", mode);
  650. } else {
  651. return -EINVAL;
  652. }
  653. return 0;
  654. }
  655. #if defined(CONFIG_CMD_PCI)
  656. #define PCI_ID(x) ( \
  657. (PCI_BUS(x->devfn)<<16)| \
  658. (PCI_DEV(x->devfn)<<11)| \
  659. (PCI_FUNC(x->devfn)<<8) \
  660. )
  661. int fdt_add_pci_node(void *blob, int par, struct pci_dev *dev)
  662. {
  663. uint32_t reg[5];
  664. char node[32];
  665. int np;
  666. sprintf(node, "pcie@%d,%d,%d", PCI_BUS(dev->devfn),
  667. PCI_DEV(dev->devfn), PCI_FUNC(dev->devfn));
  668. np = fdt_subnode_offset(blob, par, node);
  669. if (np >= 0)
  670. return np;
  671. np = fdt_add_subnode(blob, par, node);
  672. if (np < 0) {
  673. printf(" %s failed: no space\n", __func__);
  674. return np;
  675. }
  676. memset(reg, 0, sizeof(reg));
  677. reg[0] = cpu_to_fdt32(PCI_ID(dev));
  678. fdt_setprop(blob, np, "reg", reg, sizeof(reg));
  679. return np;
  680. }
  681. /* build a path of nested PCI devs for all bridges passed through */
  682. int fdt_add_pci_path(void *blob, struct pci_dev *dev)
  683. {
  684. struct pci_dev *bridges[MAX_PCI_DEVS];
  685. int k, np;
  686. /* build list of parents */
  687. np = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
  688. if (np < 0)
  689. return np;
  690. k = 0;
  691. while (dev) {
  692. bridges[k++] = dev;
  693. dev = dev->ppar;
  694. };
  695. /* now add them the to DT in reverse order */
  696. while (k--) {
  697. np = fdt_add_pci_node(blob, np, bridges[k]);
  698. if (np < 0)
  699. break;
  700. }
  701. return np;
  702. }
  703. /*
  704. * The GW16082 has a hardware errata errata such that it's
  705. * INTA/B/C/D are mis-mapped to its four slots (slot12-15). Because
  706. * of this normal PCI interrupt swizzling will not work so we will
  707. * provide an irq-map via device-tree.
  708. */
  709. int fdt_fixup_gw16082(void *blob, int np, struct pci_dev *dev)
  710. {
  711. int len;
  712. int host;
  713. uint32_t imap_new[8*4*4];
  714. const uint32_t *imap;
  715. uint32_t irq[4];
  716. uint32_t reg[4];
  717. int i;
  718. /* build irq-map based on host controllers map */
  719. host = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
  720. if (host < 0) {
  721. printf(" %s failed: missing host\n", __func__);
  722. return host;
  723. }
  724. /* use interrupt data from root complex's node */
  725. imap = fdt_getprop(blob, host, "interrupt-map", &len);
  726. if (!imap || len != 128) {
  727. printf(" %s failed: invalid interrupt-map\n",
  728. __func__);
  729. return -FDT_ERR_NOTFOUND;
  730. }
  731. /* obtain irq's of host controller in pin order */
  732. for (i = 0; i < 4; i++)
  733. irq[(fdt32_to_cpu(imap[(i*8)+3])-1)%4] = imap[(i*8)+6];
  734. /*
  735. * determine number of swizzles necessary:
  736. * For each bridge we pass through we need to swizzle
  737. * the number of the slot we are on.
  738. */
  739. struct pci_dev *d;
  740. int b;
  741. b = 0;
  742. d = dev->ppar;
  743. while(d && d->ppar) {
  744. b += PCI_DEV(d->devfn);
  745. d = d->ppar;
  746. }
  747. /* create new irq mappings for slots12-15
  748. * <skt> <idsel> <slot> <skt-inta> <skt-intb>
  749. * J3 AD28 12 INTD INTA
  750. * J4 AD29 13 INTC INTD
  751. * J5 AD30 14 INTB INTC
  752. * J2 AD31 15 INTA INTB
  753. */
  754. for (i = 0; i < 4; i++) {
  755. /* addr matches bus:dev:func */
  756. u32 addr = dev->busno << 16 | (12+i) << 11;
  757. /* default cells from root complex */
  758. memcpy(&imap_new[i*32], imap, 128);
  759. /* first cell is PCI device address (BDF) */
  760. imap_new[(i*32)+(0*8)+0] = cpu_to_fdt32(addr);
  761. imap_new[(i*32)+(1*8)+0] = cpu_to_fdt32(addr);
  762. imap_new[(i*32)+(2*8)+0] = cpu_to_fdt32(addr);
  763. imap_new[(i*32)+(3*8)+0] = cpu_to_fdt32(addr);
  764. /* third cell is pin */
  765. imap_new[(i*32)+(0*8)+3] = cpu_to_fdt32(1);
  766. imap_new[(i*32)+(1*8)+3] = cpu_to_fdt32(2);
  767. imap_new[(i*32)+(2*8)+3] = cpu_to_fdt32(3);
  768. imap_new[(i*32)+(3*8)+3] = cpu_to_fdt32(4);
  769. /* sixth cell is relative interrupt */
  770. imap_new[(i*32)+(0*8)+6] = irq[(15-(12+i)+b+0)%4];
  771. imap_new[(i*32)+(1*8)+6] = irq[(15-(12+i)+b+1)%4];
  772. imap_new[(i*32)+(2*8)+6] = irq[(15-(12+i)+b+2)%4];
  773. imap_new[(i*32)+(3*8)+6] = irq[(15-(12+i)+b+3)%4];
  774. }
  775. fdt_setprop(blob, np, "interrupt-map", imap_new,
  776. sizeof(imap_new));
  777. reg[0] = cpu_to_fdt32(0xfff00);
  778. reg[1] = 0;
  779. reg[2] = 0;
  780. reg[3] = cpu_to_fdt32(0x7);
  781. fdt_setprop(blob, np, "interrupt-map-mask", reg, sizeof(reg));
  782. fdt_setprop_cell(blob, np, "#interrupt-cells", 1);
  783. fdt_setprop_string(blob, np, "device_type", "pci");
  784. fdt_setprop_cell(blob, np, "#address-cells", 3);
  785. fdt_setprop_cell(blob, np, "#size-cells", 2);
  786. printf(" Added custom interrupt-map for GW16082\n");
  787. return 0;
  788. }
  789. /* The sky2 GigE MAC obtains it's MAC addr from device-tree by default */
  790. int fdt_fixup_sky2(void *blob, int np, struct pci_dev *dev)
  791. {
  792. char *tmp, *end;
  793. char mac[16];
  794. unsigned char mac_addr[6];
  795. int j;
  796. sprintf(mac, "eth1addr");
  797. tmp = env_get(mac);
  798. if (tmp) {
  799. for (j = 0; j < 6; j++) {
  800. mac_addr[j] = tmp ?
  801. hextoul(tmp, &end) : 0;
  802. if (tmp)
  803. tmp = (*end) ? end+1 : end;
  804. }
  805. fdt_setprop(blob, np, "local-mac-address", mac_addr,
  806. sizeof(mac_addr));
  807. printf(" Added mac addr for eth1\n");
  808. return 0;
  809. }
  810. return -1;
  811. }
  812. /*
  813. * PCI DT nodes must be nested therefore if we need to apply a DT fixup
  814. * we will walk the PCI bus and add bridge nodes up to the device receiving
  815. * the fixup.
  816. */
  817. void ft_board_pci_fixup(void *blob, struct bd_info *bd)
  818. {
  819. int i, np;
  820. struct pci_dev *dev;
  821. for (i = 0; i < pci_devno; i++) {
  822. dev = &pci_devs[i];
  823. /*
  824. * The GW16082 consists of a TI XIO2001 PCIe-to-PCI bridge and
  825. * an EEPROM at i2c1-0x50.
  826. */
  827. if ((dev->vendor == PCI_VENDOR_ID_TI) &&
  828. (dev->device == 0x8240) &&
  829. (i2c_set_bus_num(1) == 0) &&
  830. (i2c_probe(0x50) == 0))
  831. {
  832. np = fdt_add_pci_path(blob, dev);
  833. if (np > 0)
  834. fdt_fixup_gw16082(blob, np, dev);
  835. }
  836. /* ethernet1 mac address */
  837. else if ((dev->vendor == PCI_VENDOR_ID_MARVELL) &&
  838. (dev->device == 0x4380))
  839. {
  840. np = fdt_add_pci_path(blob, dev);
  841. if (np > 0)
  842. fdt_fixup_sky2(blob, np, dev);
  843. }
  844. }
  845. }
  846. #endif /* if defined(CONFIG_CMD_PCI) */
  847. /*
  848. * called prior to booting kernel or by 'fdt boardsetup' command
  849. *
  850. * unless 'fdt_noauto' env var is set we will update the following in the DTB:
  851. * - mtd partitions based on mtdparts/mtdids env
  852. * - system-serial (board serial num from EEPROM)
  853. * - board (full model from EEPROM)
  854. * - peripherals removed from DTB if not loaded on board (per EEPROM config)
  855. */
  856. #define PWM0_ADDR 0x2080000
  857. int ft_board_setup(void *blob, struct bd_info *bd)
  858. {
  859. struct ventana_board_info *info = &ventana_info;
  860. struct ventana_eeprom_config *cfg;
  861. static const struct node_info nand_nodes[] = {
  862. { "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */
  863. { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
  864. };
  865. const char *model = env_get("model");
  866. const char *display = env_get("display");
  867. int i;
  868. char rev = 0;
  869. /* determine board revision */
  870. for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
  871. if (ventana_info.model[i] >= 'A') {
  872. rev = ventana_info.model[i];
  873. break;
  874. }
  875. }
  876. if (env_get("fdt_noauto")) {
  877. puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
  878. return 0;
  879. }
  880. /* Update MTD partition nodes using info from mtdparts env var */
  881. puts(" Updating MTD partitions...\n");
  882. fdt_fixup_mtdparts(blob, nand_nodes, ARRAY_SIZE(nand_nodes));
  883. /* Update display timings from display env var */
  884. if (display) {
  885. if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"),
  886. display) >= 0)
  887. printf(" Set display timings for %s...\n", display);
  888. }
  889. printf(" Adjusting FDT per EEPROM for %s...\n", model);
  890. /* board serial number */
  891. fdt_setprop(blob, 0, "system-serial", env_get("serial#"),
  892. strlen(env_get("serial#")) + 1);
  893. /* board (model contains model from device-tree) */
  894. fdt_setprop(blob, 0, "board", info->model,
  895. strlen((const char *)info->model) + 1);
  896. /* set desired digital video capture format */
  897. ft_sethdmiinfmt(blob, env_get("hdmiinfmt"));
  898. /* early board/revision ft fixups */
  899. ft_early_fixup(blob, board_type);
  900. /* Configure DIO */
  901. for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
  902. struct dio_cfg *cfg = &gpio_cfg[board_type].dio_cfg[i];
  903. char arg[10];
  904. sprintf(arg, "dio%d", i);
  905. if (!hwconfig(arg))
  906. continue;
  907. if (hwconfig_subarg_cmp(arg, "mode", "pwm") && cfg->pwm_param)
  908. {
  909. phys_addr_t addr;
  910. int off;
  911. printf(" Enabling pwm%d for DIO%d\n",
  912. cfg->pwm_param, i);
  913. addr = PWM0_ADDR + (0x4000 * (cfg->pwm_param - 1));
  914. off = fdt_node_offset_by_compat_reg(blob,
  915. "fsl,imx6q-pwm",
  916. addr);
  917. if (off)
  918. fdt_status_okay(blob, off);
  919. }
  920. }
  921. #if defined(CONFIG_CMD_PCI)
  922. if (!env_get("nopcifixup"))
  923. ft_board_pci_fixup(blob, bd);
  924. #endif
  925. /*
  926. * Peripheral Config:
  927. * remove nodes by alias path if EEPROM config tells us the
  928. * peripheral is not loaded on the board.
  929. */
  930. if (env_get("fdt_noconfig")) {
  931. puts(" Skiping periperhal config (fdt_noconfig defined)\n");
  932. return 0;
  933. }
  934. cfg = econfig;
  935. while (cfg->name) {
  936. if (!test_bit(cfg->bit, info->config)) {
  937. fdt_del_node_and_alias(blob, cfg->dtalias ?
  938. cfg->dtalias : cfg->name);
  939. }
  940. cfg++;
  941. }
  942. return 0;
  943. }
  944. #endif /* CONFIG_OF_BOARD_SETUP */