common.c 47 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2013 Gateworks Corporation
  4. *
  5. * Author: Tim Harvey <tharvey@gateworks.com>
  6. */
  7. #include <common.h>
  8. #include <log.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/mx6-pins.h>
  11. #include <asm/arch/sys_proto.h>
  12. #include <asm/gpio.h>
  13. #include <asm/mach-imx/mxc_i2c.h>
  14. #include <env.h>
  15. #include <fsl_esdhc_imx.h>
  16. #include <hwconfig.h>
  17. #include <linux/delay.h>
  18. #include <power/pmic.h>
  19. #include <power/ltc3676_pmic.h>
  20. #include <power/pfuze100_pmic.h>
  21. #include <power/mp5416.h>
  22. #include "common.h"
  23. /* UART2: Serial Console */
  24. static iomux_v3_cfg_t const uart2_pads[] = {
  25. IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  26. IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  27. };
  28. void setup_iomux_uart(void)
  29. {
  30. SETUP_IOMUX_PADS(uart2_pads);
  31. }
  32. /* MMC */
  33. static iomux_v3_cfg_t const gw5904_emmc_pads[] = {
  34. IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  35. IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  36. IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  37. IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  38. IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  39. IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  40. IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  41. IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  42. IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  43. IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  44. IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  45. };
  46. /* 4-bit microSD on SD2 */
  47. static iomux_v3_cfg_t const gw5904_mmc_pads[] = {
  48. IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  49. IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  50. IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  51. IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  52. IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  53. IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  54. /* CD */
  55. IOMUX_PADS(PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  56. };
  57. /* 8-bit eMMC on SD2/NAND */
  58. static iomux_v3_cfg_t const gw560x_emmc_sd2_pads[] = {
  59. IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  60. IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  61. IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  62. IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  63. IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  64. IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  65. IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  66. IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  67. IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  68. IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  69. };
  70. static iomux_v3_cfg_t const usdhc3_pads[] = {
  71. IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  72. IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  73. IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  74. IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  75. IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  76. IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  77. IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  78. };
  79. /*
  80. * I2C pad configs:
  81. * I2C1: GSC
  82. * I2C2: PMIC,PCIe Switch,Clock,Mezz
  83. * I2C3: Multimedia/Expansion
  84. */
  85. static struct i2c_pads_info mx6q_i2c_pad_info[] = {
  86. {
  87. .scl = {
  88. .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
  89. .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
  90. .gp = IMX_GPIO_NR(3, 21)
  91. },
  92. .sda = {
  93. .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
  94. .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
  95. .gp = IMX_GPIO_NR(3, 28)
  96. }
  97. }, {
  98. .scl = {
  99. .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
  100. .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
  101. .gp = IMX_GPIO_NR(4, 12)
  102. },
  103. .sda = {
  104. .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
  105. .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
  106. .gp = IMX_GPIO_NR(4, 13)
  107. }
  108. }, {
  109. .scl = {
  110. .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
  111. .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
  112. .gp = IMX_GPIO_NR(1, 3)
  113. },
  114. .sda = {
  115. .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC,
  116. .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC,
  117. .gp = IMX_GPIO_NR(1, 6)
  118. }
  119. }
  120. };
  121. static struct i2c_pads_info mx6dl_i2c_pad_info[] = {
  122. {
  123. .scl = {
  124. .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
  125. .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
  126. .gp = IMX_GPIO_NR(3, 21)
  127. },
  128. .sda = {
  129. .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
  130. .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
  131. .gp = IMX_GPIO_NR(3, 28)
  132. }
  133. }, {
  134. .scl = {
  135. .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
  136. .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
  137. .gp = IMX_GPIO_NR(4, 12)
  138. },
  139. .sda = {
  140. .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
  141. .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
  142. .gp = IMX_GPIO_NR(4, 13)
  143. }
  144. }, {
  145. .scl = {
  146. .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
  147. .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
  148. .gp = IMX_GPIO_NR(1, 3)
  149. },
  150. .sda = {
  151. .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC,
  152. .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC,
  153. .gp = IMX_GPIO_NR(1, 6)
  154. }
  155. }
  156. };
  157. void setup_ventana_i2c(int i2c)
  158. {
  159. struct i2c_pads_info *p;
  160. if (is_cpu_type(MXC_CPU_MX6Q))
  161. p = &mx6q_i2c_pad_info[i2c];
  162. else
  163. p = &mx6dl_i2c_pad_info[i2c];
  164. setup_i2c(i2c, CONFIG_SYS_I2C_SPEED, 0x7f, p);
  165. }
  166. /*
  167. * Baseboard specific GPIO
  168. */
  169. static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
  170. /* IOEXP_PWREN# */
  171. IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
  172. /* IOEXP_IRQ# */
  173. IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
  174. /* GPS_SHDN */
  175. IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
  176. /* PCIESKT_WDIS# */
  177. IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
  178. };
  179. static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
  180. /* SD3_VSELECT */
  181. IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
  182. /* RS232_EN# */
  183. IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
  184. /* MSATA_EN */
  185. IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
  186. /* IOEXP_PWREN# */
  187. IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
  188. /* IOEXP_IRQ# */
  189. IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
  190. /* GPS_SHDN */
  191. IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
  192. /* USBOTG_SEL */
  193. IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
  194. /* RS485_EN */
  195. IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
  196. /* PCIESKT_WDIS# */
  197. IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
  198. };
  199. static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
  200. /* SD3_VSELECT */
  201. IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
  202. /* RS232_EN# */
  203. IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
  204. /* MSATA_EN */
  205. IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
  206. /* IOEXP_PWREN# */
  207. IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
  208. /* IOEXP_IRQ# */
  209. IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
  210. /* DIOI2C_DIS# */
  211. IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
  212. /* GPS_SHDN */
  213. IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
  214. /* RS485_EN */
  215. IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
  216. /* PCIESKT_WDIS# */
  217. IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
  218. /* J6_PWREN */
  219. IOMUX_PADS(PAD_EIM_DA15__GPIO3_IO15 | DIO_PAD_CFG),
  220. /* PCIEGBE_EN */
  221. IOMUX_PADS(PAD_EIM_DA14__GPIO3_IO14 | DIO_PAD_CFG),
  222. };
  223. static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
  224. /* SD3_VSELECT */
  225. IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
  226. /* RS232_EN# */
  227. IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
  228. /* MSATA_EN */
  229. IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
  230. /* MIPI_DIO */
  231. IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | DIO_PAD_CFG),
  232. /* RS485_EN */
  233. IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | DIO_PAD_CFG),
  234. /* IOEXP_PWREN# */
  235. IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
  236. /* IOEXP_IRQ# */
  237. IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
  238. /* DIOI2C_DIS# */
  239. IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
  240. /* RS485_EN */
  241. IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
  242. /* PCIESKT_WDIS# */
  243. IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
  244. /* J7_PWREN */
  245. IOMUX_PADS(PAD_EIM_DA15__GPIO3_IO15 | DIO_PAD_CFG),
  246. /* PCIEGBE_EN */
  247. IOMUX_PADS(PAD_EIM_DA14__GPIO3_IO14 | DIO_PAD_CFG),
  248. };
  249. static iomux_v3_cfg_t const gw551x_gpio_pads[] = {
  250. /* PCIESKT_WDIS# */
  251. IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
  252. };
  253. static iomux_v3_cfg_t const gw552x_gpio_pads[] = {
  254. /* MSATA_EN */
  255. IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
  256. /* USBOTG_SEL */
  257. IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
  258. /* MX6_DIO[4:9] */
  259. IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18 | DIO_PAD_CFG),
  260. IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
  261. IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21 | DIO_PAD_CFG),
  262. IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22 | DIO_PAD_CFG),
  263. IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23 | DIO_PAD_CFG),
  264. IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25 | DIO_PAD_CFG),
  265. /* PCIEGBE1_OFF# */
  266. IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | DIO_PAD_CFG),
  267. /* PCIEGBE2_OFF# */
  268. IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
  269. /* PCIESKT_WDIS# */
  270. IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
  271. };
  272. static iomux_v3_cfg_t const gw553x_gpio_pads[] = {
  273. /* SD3_VSELECT */
  274. IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
  275. /* PCIESKT_WDIS# */
  276. IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
  277. };
  278. static iomux_v3_cfg_t const gw560x_gpio_pads[] = {
  279. /* RS232_EN# */
  280. IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
  281. /* IOEXP_PWREN# */
  282. IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
  283. /* IOEXP_IRQ# */
  284. IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
  285. /* DIOI2C_DIS# */
  286. IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
  287. /* RS485_EN */
  288. IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
  289. /* PCIESKT_WDIS# */
  290. IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
  291. /* 12V0_PWR_EN */
  292. IOMUX_PADS(PAD_DISP0_DAT5__GPIO4_IO26 | DIO_PAD_CFG),
  293. };
  294. static iomux_v3_cfg_t const gw5901_gpio_pads[] = {
  295. /* ETH1_EN */
  296. IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | DIO_PAD_CFG),
  297. /* PMIC reset */
  298. IOMUX_PADS(PAD_DISP0_DAT8__WDOG1_B | DIO_PAD_CFG),
  299. /* COM_CFGA/B/C/D */
  300. IOMUX_PADS(PAD_DISP0_DAT20__GPIO5_IO14 | DIO_PAD_CFG),
  301. IOMUX_PADS(PAD_DISP0_DAT21__GPIO5_IO15 | DIO_PAD_CFG),
  302. IOMUX_PADS(PAD_DISP0_DAT22__GPIO5_IO16 | DIO_PAD_CFG),
  303. IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
  304. /* ETI_IRQ# */
  305. IOMUX_PADS(PAD_GPIO_5__GPIO1_IO05 | DIO_PAD_CFG),
  306. /* DIO_IRQ# */
  307. IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
  308. /* FIBER_SIGDET */
  309. IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
  310. };
  311. static iomux_v3_cfg_t const gw5902_gpio_pads[] = {
  312. /* UART1_EN# */
  313. IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
  314. /* 5V_UVLO */
  315. IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
  316. /* ETI_IRQ# */
  317. IOMUX_PADS(PAD_GPIO_5__GPIO1_IO05 | DIO_PAD_CFG),
  318. /* DIO_IRQ# */
  319. IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
  320. };
  321. static iomux_v3_cfg_t const gw5903_gpio_pads[] = {
  322. /* BKLT_12VEN */
  323. IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
  324. /* EMMY_PDN# */
  325. IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | DIO_PAD_CFG),
  326. /* EMMY_CFG1# */
  327. IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03 | DIO_PAD_CFG),
  328. /* EMMY_CFG1# */
  329. IOMUX_PADS(PAD_NANDF_D4__GPIO2_IO04 | DIO_PAD_CFG),
  330. /* USBH1_PEN (EHCI) */
  331. IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
  332. /* USBDPC_PEN */
  333. IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
  334. /* TOUCH_RST */
  335. IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | DIO_PAD_CFG),
  336. /* AUDIO_RST# */
  337. IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
  338. /* UART1_TEN# */
  339. IOMUX_PADS(PAD_CSI0_DAT12__GPIO5_IO30 | DIO_PAD_CFG),
  340. /* LVDS_BKLEN # */
  341. IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
  342. /* RGMII_PDWN# */
  343. IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | DIO_PAD_CFG),
  344. /* TOUCH_IRQ# */
  345. IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
  346. /* TOUCH_RST# */
  347. IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | DIO_PAD_CFG),
  348. };
  349. static iomux_v3_cfg_t const gw5904_gpio_pads[] = {
  350. /* IOEXP_PWREN# */
  351. IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
  352. /* IOEXP_IRQ# */
  353. IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
  354. /* DIOI2C_DIS# */
  355. IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
  356. /* UART_RS485 */
  357. IOMUX_PADS(PAD_DISP0_DAT2__GPIO4_IO23 | DIO_PAD_CFG),
  358. /* UART_HALF */
  359. IOMUX_PADS(PAD_DISP0_DAT3__GPIO4_IO24 | DIO_PAD_CFG),
  360. /* SKT1_WDIS# */
  361. IOMUX_PADS(PAD_DISP0_DAT17__GPIO5_IO11 | DIO_PAD_CFG),
  362. /* SKT1_RST# */
  363. IOMUX_PADS(PAD_DISP0_DAT18__GPIO5_IO12 | DIO_PAD_CFG),
  364. /* SKT2_WDIS# */
  365. IOMUX_PADS(PAD_DISP0_DAT19__GPIO5_IO13 | DIO_PAD_CFG),
  366. /* SKT2_RST# */
  367. IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
  368. /* M2_OFF# */
  369. IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | DIO_PAD_CFG),
  370. /* M2_WDIS# */
  371. IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14 | DIO_PAD_CFG),
  372. /* M2_RST# */
  373. IOMUX_PADS(PAD_SD2_DAT2__GPIO1_IO13 | DIO_PAD_CFG),
  374. /* RS232_EN# */
  375. IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
  376. };
  377. static iomux_v3_cfg_t const gw5905_gpio_pads[] = {
  378. /* EMMY_PDN# */
  379. IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03 | DIO_PAD_CFG),
  380. /* MIPI_RST */
  381. IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | DIO_PAD_CFG),
  382. /* MIPI_PWDN */
  383. IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14 | DIO_PAD_CFG),
  384. /* USBEHCI_SEL */
  385. IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
  386. /* LVDS_BKLEN # */
  387. IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
  388. /* PCIESKT_WDIS# */
  389. IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13 | DIO_PAD_CFG),
  390. /* SPK_SHDN# */
  391. IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
  392. /* DECT_RST# */
  393. IOMUX_PADS(PAD_DISP0_DAT20__GPIO5_IO14 | DIO_PAD_CFG),
  394. /* USBH1_PEN (EHCI) */
  395. IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
  396. /* LVDS_PWM */
  397. IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
  398. /* CODEC_RST */
  399. IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
  400. /* GYRO_CONTROL/DATA_EN */
  401. IOMUX_PADS(PAD_CSI0_DAT8__GPIO5_IO26 | DIO_PAD_CFG),
  402. /* TOUCH_RST */
  403. IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | DIO_PAD_CFG),
  404. /* TOUCH_IRQ */
  405. IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
  406. };
  407. static iomux_v3_cfg_t const gw5910_gpio_pads[] = {
  408. /* SD3_VSELECT */
  409. IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
  410. /* RS232_EN# */
  411. IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
  412. /* RF_RESET# */
  413. IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
  414. /* RF_BOOT */
  415. IOMUX_PADS(PAD_GPIO_8__GPIO1_IO08 | DIO_PAD_CFG),
  416. /* PCIESKT_WDIS# */
  417. IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
  418. };
  419. static iomux_v3_cfg_t const gw5912_gpio_pads[] = {
  420. /* SD3_VSELECT */
  421. IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
  422. /* RS232_EN# */
  423. IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
  424. /* PCIESKT_WDIS# */
  425. IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
  426. };
  427. /* Digital I/O */
  428. struct dio_cfg gw51xx_dio[] = {
  429. {
  430. { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
  431. IMX_GPIO_NR(1, 16),
  432. { 0, 0 },
  433. 0
  434. },
  435. {
  436. { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
  437. IMX_GPIO_NR(1, 19),
  438. { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
  439. 2
  440. },
  441. {
  442. { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
  443. IMX_GPIO_NR(1, 17),
  444. { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
  445. 3
  446. },
  447. {
  448. { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
  449. IMX_GPIO_NR(1, 18),
  450. { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
  451. 4
  452. },
  453. };
  454. struct dio_cfg gw52xx_dio[] = {
  455. {
  456. { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
  457. IMX_GPIO_NR(1, 16),
  458. { 0, 0 },
  459. 0
  460. },
  461. {
  462. { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
  463. IMX_GPIO_NR(1, 19),
  464. { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
  465. 2
  466. },
  467. {
  468. { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
  469. IMX_GPIO_NR(1, 17),
  470. { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
  471. 3
  472. },
  473. {
  474. { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
  475. IMX_GPIO_NR(1, 20),
  476. { 0, 0 },
  477. 0
  478. },
  479. };
  480. struct dio_cfg gw53xx_dio[] = {
  481. {
  482. { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
  483. IMX_GPIO_NR(1, 16),
  484. { 0, 0 },
  485. 0
  486. },
  487. {
  488. { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
  489. IMX_GPIO_NR(1, 19),
  490. { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
  491. 2
  492. },
  493. {
  494. { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
  495. IMX_GPIO_NR(1, 17),
  496. { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
  497. 3
  498. },
  499. {
  500. {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
  501. IMX_GPIO_NR(1, 20),
  502. { 0, 0 },
  503. 0
  504. },
  505. };
  506. struct dio_cfg gw54xx_dio[] = {
  507. {
  508. { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
  509. IMX_GPIO_NR(1, 9),
  510. { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
  511. 1
  512. },
  513. {
  514. { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
  515. IMX_GPIO_NR(1, 19),
  516. { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
  517. 2
  518. },
  519. {
  520. { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
  521. IMX_GPIO_NR(2, 9),
  522. { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
  523. 3
  524. },
  525. {
  526. { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
  527. IMX_GPIO_NR(2, 10),
  528. { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
  529. 4
  530. },
  531. };
  532. struct dio_cfg gw551x_dio[] = {
  533. {
  534. { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
  535. IMX_GPIO_NR(1, 19),
  536. { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
  537. 2
  538. },
  539. {
  540. { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
  541. IMX_GPIO_NR(1, 17),
  542. { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
  543. 3
  544. },
  545. };
  546. struct dio_cfg gw552x_dio[] = {
  547. {
  548. { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
  549. IMX_GPIO_NR(1, 16),
  550. { 0, 0 },
  551. 0
  552. },
  553. {
  554. { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
  555. IMX_GPIO_NR(1, 19),
  556. { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
  557. 2
  558. },
  559. {
  560. { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
  561. IMX_GPIO_NR(1, 17),
  562. { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
  563. 3
  564. },
  565. {
  566. {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
  567. IMX_GPIO_NR(1, 20),
  568. { 0, 0 },
  569. 0
  570. },
  571. {
  572. {IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18) },
  573. IMX_GPIO_NR(5, 18),
  574. { 0, 0 },
  575. 0
  576. },
  577. {
  578. {IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20) },
  579. IMX_GPIO_NR(5, 20),
  580. { 0, 0 },
  581. 0
  582. },
  583. {
  584. {IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21) },
  585. IMX_GPIO_NR(5, 21),
  586. { 0, 0 },
  587. 0
  588. },
  589. {
  590. {IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22) },
  591. IMX_GPIO_NR(5, 22),
  592. { 0, 0 },
  593. 0
  594. },
  595. {
  596. {IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23) },
  597. IMX_GPIO_NR(5, 23),
  598. { 0, 0 },
  599. 0
  600. },
  601. {
  602. {IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25) },
  603. IMX_GPIO_NR(5, 25),
  604. { 0, 0 },
  605. 0
  606. },
  607. };
  608. struct dio_cfg gw553x_dio[] = {
  609. {
  610. { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
  611. IMX_GPIO_NR(1, 16),
  612. { 0, 0 },
  613. 0
  614. },
  615. {
  616. { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
  617. IMX_GPIO_NR(1, 19),
  618. { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
  619. 2
  620. },
  621. {
  622. { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
  623. IMX_GPIO_NR(1, 17),
  624. { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
  625. 3
  626. },
  627. {
  628. { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
  629. IMX_GPIO_NR(1, 18),
  630. { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
  631. 4
  632. },
  633. };
  634. struct dio_cfg gw560x_dio[] = {
  635. {
  636. { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
  637. IMX_GPIO_NR(1, 16),
  638. { 0, 0 },
  639. 0
  640. },
  641. {
  642. { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
  643. IMX_GPIO_NR(1, 19),
  644. { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
  645. 2
  646. },
  647. {
  648. { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
  649. IMX_GPIO_NR(1, 17),
  650. { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
  651. 3
  652. },
  653. {
  654. {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
  655. IMX_GPIO_NR(1, 20),
  656. { 0, 0 },
  657. 0
  658. },
  659. };
  660. struct dio_cfg gw5901_dio[] = {
  661. {
  662. { IOMUX_PADS(PAD_DISP0_DAT20__GPIO5_IO14) },
  663. IMX_GPIO_NR(5, 14),
  664. { 0, 0 },
  665. 0
  666. },
  667. {
  668. { IOMUX_PADS(PAD_DISP0_DAT21__GPIO5_IO15) },
  669. IMX_GPIO_NR(5, 15),
  670. { 0, 0 },
  671. 0
  672. },
  673. {
  674. { IOMUX_PADS(PAD_DISP0_DAT22__GPIO5_IO16) },
  675. IMX_GPIO_NR(5, 16),
  676. { 0, 0 },
  677. 0
  678. },
  679. {
  680. { IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17) },
  681. IMX_GPIO_NR(5, 17),
  682. { 0, 0 },
  683. 0
  684. },
  685. };
  686. struct dio_cfg gw5902_dio[] = {
  687. {
  688. { IOMUX_PADS(PAD_DISP0_DAT20__GPIO5_IO14) },
  689. IMX_GPIO_NR(5, 14),
  690. { 0, 0 },
  691. 0
  692. },
  693. {
  694. { IOMUX_PADS(PAD_DISP0_DAT21__GPIO5_IO15) },
  695. IMX_GPIO_NR(5, 15),
  696. { 0, 0 },
  697. 0
  698. },
  699. {
  700. { IOMUX_PADS(PAD_DISP0_DAT22__GPIO5_IO16) },
  701. IMX_GPIO_NR(5, 16),
  702. { 0, 0 },
  703. 0
  704. },
  705. {
  706. { IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17) },
  707. IMX_GPIO_NR(5, 17),
  708. { 0, 0 },
  709. 0
  710. },
  711. };
  712. struct dio_cfg gw5903_dio[] = {
  713. };
  714. struct dio_cfg gw5904_dio[] = {
  715. {
  716. { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
  717. IMX_GPIO_NR(1, 16),
  718. { 0, 0 },
  719. 0
  720. },
  721. {
  722. { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
  723. IMX_GPIO_NR(1, 19),
  724. { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
  725. 2
  726. },
  727. {
  728. { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
  729. IMX_GPIO_NR(1, 17),
  730. { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
  731. 3
  732. },
  733. {
  734. {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
  735. IMX_GPIO_NR(1, 20),
  736. { 0, 0 },
  737. 0
  738. },
  739. {
  740. {IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00) },
  741. IMX_GPIO_NR(2, 0),
  742. { 0, 0 },
  743. 0
  744. },
  745. {
  746. {IOMUX_PADS(PAD_NANDF_D1__GPIO2_IO01) },
  747. IMX_GPIO_NR(2, 1),
  748. { 0, 0 },
  749. 0
  750. },
  751. {
  752. {IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02) },
  753. IMX_GPIO_NR(2, 2),
  754. { 0, 0 },
  755. 0
  756. },
  757. {
  758. {IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03) },
  759. IMX_GPIO_NR(2, 3),
  760. { 0, 0 },
  761. 0
  762. },
  763. {
  764. {IOMUX_PADS(PAD_NANDF_D4__GPIO2_IO04) },
  765. IMX_GPIO_NR(2, 4),
  766. { 0, 0 },
  767. 0
  768. },
  769. {
  770. {IOMUX_PADS(PAD_NANDF_D5__GPIO2_IO05) },
  771. IMX_GPIO_NR(2, 5),
  772. { 0, 0 },
  773. 0
  774. },
  775. {
  776. {IOMUX_PADS(PAD_NANDF_D6__GPIO2_IO06) },
  777. IMX_GPIO_NR(2, 6),
  778. { 0, 0 },
  779. 0
  780. },
  781. {
  782. {IOMUX_PADS(PAD_NANDF_D7__GPIO2_IO07) },
  783. IMX_GPIO_NR(2, 7),
  784. { 0, 0 },
  785. 0
  786. },
  787. };
  788. struct dio_cfg gw5906_dio[] = {
  789. {
  790. { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
  791. IMX_GPIO_NR(1, 16),
  792. { 0, 0 },
  793. 0
  794. },
  795. {
  796. { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
  797. IMX_GPIO_NR(1, 19),
  798. { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
  799. 2
  800. },
  801. {
  802. { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
  803. IMX_GPIO_NR(1, 17),
  804. { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
  805. 3
  806. },
  807. {
  808. {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
  809. IMX_GPIO_NR(1, 20),
  810. { 0, 0 },
  811. 0
  812. },
  813. };
  814. struct dio_cfg gw5913_dio[] = {
  815. {
  816. { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
  817. IMX_GPIO_NR(1, 16),
  818. { 0, 0 },
  819. 0
  820. },
  821. {
  822. { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
  823. IMX_GPIO_NR(1, 19),
  824. { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
  825. 2
  826. },
  827. {
  828. { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
  829. IMX_GPIO_NR(1, 17),
  830. { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
  831. 3
  832. },
  833. {
  834. { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
  835. IMX_GPIO_NR(1, 18),
  836. { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
  837. 4
  838. },
  839. {
  840. { IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15) },
  841. IMX_GPIO_NR(1, 15),
  842. { 0, 0 },
  843. 0
  844. },
  845. {
  846. { IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14) },
  847. IMX_GPIO_NR(1, 14),
  848. { 0, 0 },
  849. 0
  850. },
  851. {
  852. { IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05) },
  853. IMX_GPIO_NR(4, 5),
  854. { 0, 0 },
  855. 0
  856. },
  857. };
  858. /*
  859. * Board Specific GPIO
  860. */
  861. struct ventana gpio_cfg[GW_UNKNOWN] = {
  862. /* GW5400proto */
  863. {
  864. .gpio_pads = gw54xx_gpio_pads,
  865. .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
  866. .dio_cfg = gw54xx_dio,
  867. .dio_num = ARRAY_SIZE(gw54xx_dio),
  868. .mezz_pwren = IMX_GPIO_NR(4, 7),
  869. .mezz_irq = IMX_GPIO_NR(4, 9),
  870. .rs485en = IMX_GPIO_NR(3, 24),
  871. .dioi2c_en = IMX_GPIO_NR(4, 5),
  872. .pcie_sson = IMX_GPIO_NR(1, 20),
  873. .mmc_cd = IMX_GPIO_NR(7, 0),
  874. .wdis = -1,
  875. },
  876. /* GW51xx */
  877. {
  878. .gpio_pads = gw51xx_gpio_pads,
  879. .num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2,
  880. .dio_cfg = gw51xx_dio,
  881. .dio_num = ARRAY_SIZE(gw51xx_dio),
  882. .mezz_pwren = IMX_GPIO_NR(2, 19),
  883. .mezz_irq = IMX_GPIO_NR(2, 18),
  884. .gps_shdn = IMX_GPIO_NR(1, 2),
  885. .wdis = IMX_GPIO_NR(7, 12),
  886. },
  887. /* GW52xx */
  888. {
  889. .gpio_pads = gw52xx_gpio_pads,
  890. .num_pads = ARRAY_SIZE(gw52xx_gpio_pads)/2,
  891. .dio_cfg = gw52xx_dio,
  892. .dio_num = ARRAY_SIZE(gw52xx_dio),
  893. .mezz_pwren = IMX_GPIO_NR(2, 19),
  894. .mezz_irq = IMX_GPIO_NR(2, 18),
  895. .gps_shdn = IMX_GPIO_NR(1, 27),
  896. .usb_sel = IMX_GPIO_NR(1, 2),
  897. .wdis = IMX_GPIO_NR(7, 12),
  898. .msata_en = GP_MSATA_SEL,
  899. .rs232_en = GP_RS232_EN,
  900. .vsel_pin = IMX_GPIO_NR(6, 14),
  901. .mmc_cd = IMX_GPIO_NR(7, 0),
  902. },
  903. /* GW53xx */
  904. {
  905. .gpio_pads = gw53xx_gpio_pads,
  906. .num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2,
  907. .dio_cfg = gw53xx_dio,
  908. .dio_num = ARRAY_SIZE(gw53xx_dio),
  909. .mezz_pwren = IMX_GPIO_NR(2, 19),
  910. .mezz_irq = IMX_GPIO_NR(2, 18),
  911. .gps_shdn = IMX_GPIO_NR(1, 27),
  912. .wdis = IMX_GPIO_NR(7, 12),
  913. .msata_en = GP_MSATA_SEL,
  914. .rs232_en = GP_RS232_EN,
  915. .vsel_pin = IMX_GPIO_NR(6, 14),
  916. .mmc_cd = IMX_GPIO_NR(7, 0),
  917. },
  918. /* GW54xx */
  919. {
  920. .gpio_pads = gw54xx_gpio_pads,
  921. .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
  922. .dio_cfg = gw54xx_dio,
  923. .dio_num = ARRAY_SIZE(gw54xx_dio),
  924. .mezz_pwren = IMX_GPIO_NR(2, 19),
  925. .mezz_irq = IMX_GPIO_NR(2, 18),
  926. .rs485en = IMX_GPIO_NR(7, 1),
  927. .dioi2c_en = IMX_GPIO_NR(4, 5),
  928. .pcie_sson = IMX_GPIO_NR(1, 20),
  929. .wdis = IMX_GPIO_NR(5, 17),
  930. .msata_en = GP_MSATA_SEL,
  931. .rs232_en = GP_RS232_EN,
  932. .vsel_pin = IMX_GPIO_NR(6, 14),
  933. .mmc_cd = IMX_GPIO_NR(7, 0),
  934. },
  935. /* GW551x */
  936. {
  937. .gpio_pads = gw551x_gpio_pads,
  938. .num_pads = ARRAY_SIZE(gw551x_gpio_pads)/2,
  939. .dio_cfg = gw551x_dio,
  940. .dio_num = ARRAY_SIZE(gw551x_dio),
  941. .wdis = IMX_GPIO_NR(7, 12),
  942. },
  943. /* GW552x */
  944. {
  945. .gpio_pads = gw552x_gpio_pads,
  946. .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2,
  947. .dio_cfg = gw552x_dio,
  948. .dio_num = ARRAY_SIZE(gw552x_dio),
  949. .usb_sel = IMX_GPIO_NR(1, 7),
  950. .wdis = IMX_GPIO_NR(7, 12),
  951. .msata_en = GP_MSATA_SEL,
  952. },
  953. /* GW553x */
  954. {
  955. .gpio_pads = gw553x_gpio_pads,
  956. .num_pads = ARRAY_SIZE(gw553x_gpio_pads)/2,
  957. .dio_cfg = gw553x_dio,
  958. .dio_num = ARRAY_SIZE(gw553x_dio),
  959. .wdis = IMX_GPIO_NR(7, 12),
  960. .vsel_pin = IMX_GPIO_NR(6, 14),
  961. .mmc_cd = IMX_GPIO_NR(7, 0),
  962. },
  963. /* GW560x */
  964. {
  965. .gpio_pads = gw560x_gpio_pads,
  966. .num_pads = ARRAY_SIZE(gw560x_gpio_pads)/2,
  967. .dio_cfg = gw560x_dio,
  968. .dio_num = ARRAY_SIZE(gw560x_dio),
  969. .mezz_pwren = IMX_GPIO_NR(2, 19),
  970. .mezz_irq = IMX_GPIO_NR(2, 18),
  971. .rs232_en = GP_RS232_EN,
  972. .wdis = IMX_GPIO_NR(7, 12),
  973. .mmc_cd = IMX_GPIO_NR(7, 0),
  974. },
  975. /* GW5901 */
  976. {
  977. .gpio_pads = gw5901_gpio_pads,
  978. .num_pads = ARRAY_SIZE(gw5901_gpio_pads)/2,
  979. .dio_cfg = gw5901_dio,
  980. .wdis = -1,
  981. },
  982. /* GW5902 */
  983. {
  984. .gpio_pads = gw5902_gpio_pads,
  985. .num_pads = ARRAY_SIZE(gw5902_gpio_pads)/2,
  986. .dio_cfg = gw5902_dio,
  987. .rs232_en = GP_RS232_EN,
  988. .wdis = -1,
  989. },
  990. /* GW5903 */
  991. {
  992. .gpio_pads = gw5903_gpio_pads,
  993. .num_pads = ARRAY_SIZE(gw5903_gpio_pads)/2,
  994. .dio_cfg = gw5903_dio,
  995. .dio_num = ARRAY_SIZE(gw5903_dio),
  996. .mmc_cd = IMX_GPIO_NR(6, 11),
  997. .wdis = -1,
  998. },
  999. /* GW5904 */
  1000. {
  1001. .gpio_pads = gw5904_gpio_pads,
  1002. .num_pads = ARRAY_SIZE(gw5904_gpio_pads)/2,
  1003. .dio_cfg = gw5904_dio,
  1004. .dio_num = ARRAY_SIZE(gw5904_dio),
  1005. .mezz_pwren = IMX_GPIO_NR(2, 19),
  1006. .mezz_irq = IMX_GPIO_NR(2, 18),
  1007. .wdis = -1,
  1008. },
  1009. /* GW5905 */
  1010. {
  1011. .gpio_pads = gw5905_gpio_pads,
  1012. .num_pads = ARRAY_SIZE(gw5905_gpio_pads)/2,
  1013. .wdis = IMX_GPIO_NR(7, 13),
  1014. },
  1015. /* GW5906 */
  1016. {
  1017. .gpio_pads = gw552x_gpio_pads,
  1018. .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2,
  1019. .dio_cfg = gw5906_dio,
  1020. .dio_num = ARRAY_SIZE(gw5906_dio),
  1021. .usb_sel = IMX_GPIO_NR(1, 7),
  1022. .wdis = IMX_GPIO_NR(7, 12),
  1023. .msata_en = GP_MSATA_SEL,
  1024. },
  1025. /* GW5907 */
  1026. {
  1027. .gpio_pads = gw51xx_gpio_pads,
  1028. .num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2,
  1029. .dio_cfg = gw51xx_dio,
  1030. .dio_num = ARRAY_SIZE(gw51xx_dio),
  1031. .wdis = IMX_GPIO_NR(7, 12),
  1032. },
  1033. /* GW5908 */
  1034. {
  1035. .gpio_pads = gw53xx_gpio_pads,
  1036. .num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2,
  1037. .dio_cfg = gw53xx_dio,
  1038. .dio_num = ARRAY_SIZE(gw53xx_dio),
  1039. .mezz_pwren = IMX_GPIO_NR(2, 19),
  1040. .mezz_irq = IMX_GPIO_NR(2, 18),
  1041. .gps_shdn = IMX_GPIO_NR(1, 27),
  1042. .wdis = IMX_GPIO_NR(7, 12),
  1043. .msata_en = GP_MSATA_SEL,
  1044. .rs232_en = GP_RS232_EN,
  1045. },
  1046. /* GW5909 */
  1047. {
  1048. .gpio_pads = gw5904_gpio_pads,
  1049. .num_pads = ARRAY_SIZE(gw5904_gpio_pads)/2,
  1050. .dio_cfg = gw5904_dio,
  1051. .dio_num = ARRAY_SIZE(gw5904_dio),
  1052. .mezz_pwren = IMX_GPIO_NR(2, 19),
  1053. .mezz_irq = IMX_GPIO_NR(2, 18),
  1054. .wdis = -1,
  1055. },
  1056. /* GW5910 */
  1057. {
  1058. .gpio_pads = gw5910_gpio_pads,
  1059. .num_pads = ARRAY_SIZE(gw5910_gpio_pads) / 2,
  1060. .dio_cfg = gw52xx_dio,
  1061. .dio_num = ARRAY_SIZE(gw52xx_dio),
  1062. .wdis = IMX_GPIO_NR(7, 12),
  1063. .rs232_en = GP_RS232_EN,
  1064. .vsel_pin = IMX_GPIO_NR(6, 14),
  1065. .mmc_cd = IMX_GPIO_NR(7, 0),
  1066. },
  1067. /* GW5912 */
  1068. {
  1069. .gpio_pads = gw5912_gpio_pads,
  1070. .num_pads = ARRAY_SIZE(gw5912_gpio_pads) / 2,
  1071. .dio_cfg = gw54xx_dio,
  1072. .dio_num = ARRAY_SIZE(gw54xx_dio),
  1073. .wdis = IMX_GPIO_NR(1, 0),
  1074. .rs232_en = GP_RS232_EN,
  1075. .vsel_pin = IMX_GPIO_NR(6, 14),
  1076. .mmc_cd = IMX_GPIO_NR(7, 0),
  1077. },
  1078. /* GW5913 */
  1079. {
  1080. .gpio_pads = gw5912_gpio_pads,
  1081. .num_pads = ARRAY_SIZE(gw5912_gpio_pads) / 2,
  1082. .dio_cfg = gw5913_dio,
  1083. .dio_num = ARRAY_SIZE(gw5913_dio),
  1084. .wdis = IMX_GPIO_NR(1, 0),
  1085. },
  1086. };
  1087. #define SETUP_GPIO_OUTPUT(gpio, name, level) \
  1088. gpio_request(gpio, name); \
  1089. gpio_direction_output(gpio, level);
  1090. #define SETUP_GPIO_INPUT(gpio, name) \
  1091. gpio_request(gpio, name); \
  1092. gpio_direction_input(gpio);
  1093. void setup_iomux_gpio(int board, struct ventana_board_info *info)
  1094. {
  1095. if (board >= GW_UNKNOWN)
  1096. return;
  1097. /* board specific iomux */
  1098. imx_iomux_v3_setup_multiple_pads(gpio_cfg[board].gpio_pads,
  1099. gpio_cfg[board].num_pads);
  1100. /* RS232_EN# */
  1101. if (gpio_cfg[board].rs232_en) {
  1102. gpio_request(gpio_cfg[board].rs232_en, "rs232_en#");
  1103. gpio_direction_output(gpio_cfg[board].rs232_en, 0);
  1104. }
  1105. /* MSATA Enable - default to PCI */
  1106. if (gpio_cfg[board].msata_en) {
  1107. gpio_request(gpio_cfg[board].msata_en, "msata_en");
  1108. gpio_direction_output(gpio_cfg[board].msata_en, 0);
  1109. }
  1110. /* Expansion Mezzanine IO */
  1111. if (gpio_cfg[board].mezz_pwren) {
  1112. gpio_request(gpio_cfg[board].mezz_pwren, "mezz_pwr");
  1113. gpio_direction_output(gpio_cfg[board].mezz_pwren, 0);
  1114. }
  1115. if (gpio_cfg[board].mezz_irq) {
  1116. gpio_request(gpio_cfg[board].mezz_irq, "mezz_irq#");
  1117. gpio_direction_input(gpio_cfg[board].mezz_irq);
  1118. }
  1119. /* RS485 Transmit Enable */
  1120. if (gpio_cfg[board].rs485en) {
  1121. gpio_request(gpio_cfg[board].rs485en, "rs485_en");
  1122. gpio_direction_output(gpio_cfg[board].rs485en, 0);
  1123. }
  1124. /* GPS_SHDN */
  1125. if (gpio_cfg[board].gps_shdn) {
  1126. gpio_request(gpio_cfg[board].gps_shdn, "gps_shdn");
  1127. gpio_direction_output(gpio_cfg[board].gps_shdn, 1);
  1128. }
  1129. /* DIOI2C_DIS# */
  1130. if (gpio_cfg[board].dioi2c_en) {
  1131. gpio_request(gpio_cfg[board].dioi2c_en, "dioi2c_dis#");
  1132. gpio_direction_output(gpio_cfg[board].dioi2c_en, 0);
  1133. }
  1134. /* PCICK_SSON: disable spread-spectrum clock */
  1135. if (gpio_cfg[board].pcie_sson) {
  1136. gpio_request(gpio_cfg[board].pcie_sson, "pci_sson");
  1137. gpio_direction_output(gpio_cfg[board].pcie_sson, 0);
  1138. }
  1139. /* USBOTG mux routing */
  1140. if (gpio_cfg[board].usb_sel) {
  1141. gpio_request(gpio_cfg[board].usb_sel, "usb_pcisel");
  1142. gpio_direction_output(gpio_cfg[board].usb_sel, 0);
  1143. }
  1144. /* PCISKT_WDIS# (Wireless disable GPIO to miniPCIe sockets) */
  1145. if (gpio_cfg[board].wdis != -1) {
  1146. gpio_request(gpio_cfg[board].wdis, "wlan_dis");
  1147. gpio_direction_output(gpio_cfg[board].wdis, 1);
  1148. }
  1149. /* sense vselect pin to see if we support uhs-i */
  1150. if (gpio_cfg[board].vsel_pin) {
  1151. gpio_request(gpio_cfg[board].vsel_pin, "sd3_vselect");
  1152. gpio_direction_input(gpio_cfg[board].vsel_pin);
  1153. gpio_cfg[board].usd_vsel = !gpio_get_value(gpio_cfg[board].vsel_pin);
  1154. }
  1155. /* microSD CD */
  1156. if (gpio_cfg[board].mmc_cd) {
  1157. gpio_request(gpio_cfg[board].mmc_cd, "sd_cd");
  1158. gpio_direction_input(gpio_cfg[board].mmc_cd);
  1159. }
  1160. /* Anything else board specific */
  1161. switch(board) {
  1162. case GW53xx:
  1163. gpio_request(IMX_GPIO_NR(3, 15), "j6_pwren");
  1164. gpio_direction_output(IMX_GPIO_NR(3, 15), 1);
  1165. gpio_request(IMX_GPIO_NR(3, 14), "gbe_en");
  1166. gpio_direction_output(IMX_GPIO_NR(3, 14), 1);
  1167. break;
  1168. case GW54xx:
  1169. gpio_request(IMX_GPIO_NR(3, 15), "j7_pwren");
  1170. gpio_direction_output(IMX_GPIO_NR(3, 15), 1);
  1171. gpio_request(IMX_GPIO_NR(3, 14), "gbe_en");
  1172. gpio_direction_output(IMX_GPIO_NR(3, 14), 1);
  1173. break;
  1174. case GW560x:
  1175. gpio_request(IMX_GPIO_NR(4, 26), "12p0_en");
  1176. gpio_direction_output(IMX_GPIO_NR(4, 26), 1);
  1177. break;
  1178. case GW5902:
  1179. SETUP_GPIO_OUTPUT(IMX_GPIO_NR(7, 12), "5P0V_EN", 1);
  1180. break;
  1181. case GW5903:
  1182. gpio_request(IMX_GPIO_NR(3, 31) , "usbh1-ehci_pwr");
  1183. gpio_direction_output(IMX_GPIO_NR(3, 31), 1);
  1184. gpio_request(IMX_GPIO_NR(4, 15) , "usbh2-otg_pwr");
  1185. gpio_direction_output(IMX_GPIO_NR(4, 15), 1);
  1186. gpio_request(IMX_GPIO_NR(4, 7) , "usbdpc_pwr");
  1187. gpio_direction_output(IMX_GPIO_NR(4, 15), 1);
  1188. gpio_request(IMX_GPIO_NR(1, 25) , "rgmii_en");
  1189. gpio_direction_output(IMX_GPIO_NR(1, 25), 1);
  1190. gpio_request(IMX_GPIO_NR(4, 6) , "touch_irq#");
  1191. gpio_direction_input(IMX_GPIO_NR(4, 6));
  1192. gpio_request(IMX_GPIO_NR(4, 8) , "touch_rst");
  1193. gpio_direction_output(IMX_GPIO_NR(4, 8), 1);
  1194. gpio_request(IMX_GPIO_NR(1, 7) , "bklt_12ven");
  1195. gpio_direction_output(IMX_GPIO_NR(1, 7), 1);
  1196. break;
  1197. case GW5909:
  1198. case GW5904:
  1199. gpio_request(IMX_GPIO_NR(4, 23), "rs485_en");
  1200. gpio_direction_output(IMX_GPIO_NR(4, 23), 0);
  1201. gpio_request(IMX_GPIO_NR(5, 11), "skt1_wdis#");
  1202. gpio_direction_output(IMX_GPIO_NR(5, 11), 1);
  1203. gpio_request(IMX_GPIO_NR(5, 12), "skt1_rst#");
  1204. gpio_direction_output(IMX_GPIO_NR(5, 12), 1);
  1205. gpio_request(IMX_GPIO_NR(5, 13), "skt2_wdis#");
  1206. gpio_direction_output(IMX_GPIO_NR(5, 13), 1);
  1207. gpio_request(IMX_GPIO_NR(1, 15), "m2_off#");
  1208. gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
  1209. gpio_request(IMX_GPIO_NR(1, 14), "m2_wdis#");
  1210. gpio_direction_output(IMX_GPIO_NR(1, 14), 1);
  1211. gpio_request(IMX_GPIO_NR(1, 13), "m2_rst#");
  1212. gpio_direction_output(IMX_GPIO_NR(1, 13), 1);
  1213. break;
  1214. case GW5905:
  1215. SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 7), "usb_pcisel", 0);
  1216. SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 9), "lvds_cabc", 1);
  1217. SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 14), "mipi_pdwn", 1);
  1218. SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 15), "mipi_rst#", 0);
  1219. SETUP_GPIO_OUTPUT(IMX_GPIO_NR(2, 3), "emmy_pdwn#", 1);
  1220. SETUP_GPIO_OUTPUT(IMX_GPIO_NR(4, 5), "spk_shdn#", 0);
  1221. SETUP_GPIO_OUTPUT(IMX_GPIO_NR(4, 8), "touch_rst", 0);
  1222. SETUP_GPIO_OUTPUT(IMX_GPIO_NR(4, 6), "touch_irq", 0);
  1223. SETUP_GPIO_OUTPUT(IMX_GPIO_NR(5, 5), "flash_en1", 0);
  1224. SETUP_GPIO_OUTPUT(IMX_GPIO_NR(5, 6), "flash_en2", 0);
  1225. SETUP_GPIO_OUTPUT(IMX_GPIO_NR(5, 14), "dect_rst#", 1);
  1226. SETUP_GPIO_OUTPUT(IMX_GPIO_NR(5, 17), "codec_rst#", 0);
  1227. SETUP_GPIO_OUTPUT(IMX_GPIO_NR(5, 26), "imu_den", 1);
  1228. SETUP_GPIO_OUTPUT(IMX_GPIO_NR(7, 12), "lvds_cabc", 0);
  1229. mdelay(100);
  1230. /*
  1231. * gauruntee touch controller comes out of reset with INT
  1232. * low for address
  1233. */
  1234. SETUP_GPIO_OUTPUT(IMX_GPIO_NR(4, 8), "touch_rst", 1);
  1235. break;
  1236. case GW5910:
  1237. /* CC1352 */
  1238. SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 7), "rf_reset#", 1);
  1239. SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 8), "rf_boot", 1);
  1240. break;
  1241. }
  1242. }
  1243. /* setup GPIO pinmux and default configuration per baseboard and env */
  1244. void setup_board_gpio(int board, struct ventana_board_info *info)
  1245. {
  1246. const char *s;
  1247. char arg[10];
  1248. size_t len;
  1249. int i;
  1250. int quiet = simple_strtol(env_get("quiet"), NULL, 10);
  1251. if (board >= GW_UNKNOWN)
  1252. return;
  1253. /* RS232_EN# */
  1254. if (gpio_cfg[board].rs232_en) {
  1255. gpio_direction_output(gpio_cfg[board].rs232_en,
  1256. (hwconfig("rs232")) ? 0 : 1);
  1257. }
  1258. /* MSATA Enable */
  1259. if (gpio_cfg[board].msata_en && is_cpu_type(MXC_CPU_MX6Q)) {
  1260. gpio_direction_output(GP_MSATA_SEL,
  1261. (hwconfig("msata")) ? 1 : 0);
  1262. }
  1263. /* USBOTG Select (PCISKT or FrontPanel) */
  1264. if (gpio_cfg[board].usb_sel) {
  1265. gpio_direction_output(gpio_cfg[board].usb_sel,
  1266. (hwconfig("usb_pcisel")) ? 1 : 0);
  1267. }
  1268. /*
  1269. * Configure DIO pinmux/padctl registers
  1270. * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions
  1271. */
  1272. for (i = 0; i < gpio_cfg[board].dio_num; i++) {
  1273. struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i];
  1274. iomux_v3_cfg_t ctrl = DIO_PAD_CFG;
  1275. unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1;
  1276. if (!cfg->gpio_padmux[0] && !cfg->gpio_padmux[1])
  1277. continue;
  1278. sprintf(arg, "dio%d", i);
  1279. if (!hwconfig(arg))
  1280. continue;
  1281. s = hwconfig_subarg(arg, "padctrl", &len);
  1282. if (s) {
  1283. ctrl = MUX_PAD_CTRL(hextoul(s, NULL)
  1284. & 0x1ffff) | MUX_MODE_SION;
  1285. }
  1286. if (hwconfig_subarg_cmp(arg, "mode", "gpio")) {
  1287. if (!quiet) {
  1288. printf("DIO%d: GPIO%d_IO%02d (gpio-%d)\n", i,
  1289. (cfg->gpio_param/32)+1,
  1290. cfg->gpio_param%32,
  1291. cfg->gpio_param);
  1292. }
  1293. imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] |
  1294. ctrl);
  1295. gpio_requestf(cfg->gpio_param, "dio%d", i);
  1296. gpio_direction_input(cfg->gpio_param);
  1297. } else if (hwconfig_subarg_cmp(arg, "mode", "pwm") &&
  1298. cfg->pwm_padmux) {
  1299. if (!cfg->pwm_param) {
  1300. printf("DIO%d: Error: pwm config invalid\n",
  1301. i);
  1302. continue;
  1303. }
  1304. if (!quiet)
  1305. printf("DIO%d: pwm%d\n", i, cfg->pwm_param);
  1306. imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] |
  1307. MUX_PAD_CTRL(ctrl));
  1308. }
  1309. }
  1310. if (!quiet) {
  1311. if (gpio_cfg[board].msata_en && is_cpu_type(MXC_CPU_MX6Q)) {
  1312. printf("MSATA: %s\n", (hwconfig("msata") ?
  1313. "enabled" : "disabled"));
  1314. }
  1315. if (gpio_cfg[board].rs232_en) {
  1316. printf("RS232: %s\n", (hwconfig("rs232")) ?
  1317. "enabled" : "disabled");
  1318. }
  1319. }
  1320. }
  1321. /* setup board specific PMIC */
  1322. void setup_pmic(void)
  1323. {
  1324. struct pmic *p;
  1325. struct ventana_board_info ventana_info;
  1326. int board = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
  1327. const int i2c_pmic = 1;
  1328. u32 reg;
  1329. char rev;
  1330. int i;
  1331. /* determine board revision */
  1332. rev = 'A';
  1333. for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
  1334. if (ventana_info.model[i] >= 'A') {
  1335. rev = ventana_info.model[i];
  1336. break;
  1337. }
  1338. }
  1339. i2c_set_bus_num(i2c_pmic);
  1340. /* configure PFUZE100 PMIC */
  1341. if (!i2c_probe(CONFIG_POWER_PFUZE100_I2C_ADDR)) {
  1342. debug("probed PFUZE100@0x%x\n", CONFIG_POWER_PFUZE100_I2C_ADDR);
  1343. power_pfuze100_init(i2c_pmic);
  1344. p = pmic_get("PFUZE100");
  1345. if (p && !pmic_probe(p)) {
  1346. pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
  1347. printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
  1348. /* Set VGEN1 to 1.5V and enable */
  1349. pmic_reg_read(p, PFUZE100_VGEN1VOL, &reg);
  1350. reg &= ~(LDO_VOL_MASK);
  1351. reg |= (LDOA_1_50V | LDO_EN);
  1352. pmic_reg_write(p, PFUZE100_VGEN1VOL, reg);
  1353. /* Set SWBST to 5.0V and enable */
  1354. pmic_reg_read(p, PFUZE100_SWBSTCON1, &reg);
  1355. reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
  1356. reg |= (SWBST_5_00V | (SWBST_MODE_AUTO << SWBST_MODE_SHIFT));
  1357. pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
  1358. if (board == GW54xx && (rev == 'G')) {
  1359. /* Disable VGEN5 */
  1360. pmic_reg_write(p, PFUZE100_VGEN5VOL, 0);
  1361. /* Set VGEN6 to 2.5V and enable */
  1362. pmic_reg_read(p, PFUZE100_VGEN6VOL, &reg);
  1363. reg &= ~(LDO_VOL_MASK);
  1364. reg |= (LDOB_2_50V | LDO_EN);
  1365. pmic_reg_write(p, PFUZE100_VGEN6VOL, reg);
  1366. }
  1367. }
  1368. /* put all switchers in continuous mode */
  1369. pmic_reg_read(p, PFUZE100_SW1ABMODE, &reg);
  1370. reg &= ~(SW_MODE_MASK);
  1371. reg |= PWM_PWM;
  1372. pmic_reg_write(p, PFUZE100_SW1ABMODE, reg);
  1373. pmic_reg_read(p, PFUZE100_SW2MODE, &reg);
  1374. reg &= ~(SW_MODE_MASK);
  1375. reg |= PWM_PWM;
  1376. pmic_reg_write(p, PFUZE100_SW2MODE, reg);
  1377. pmic_reg_read(p, PFUZE100_SW3AMODE, &reg);
  1378. reg &= ~(SW_MODE_MASK);
  1379. reg |= PWM_PWM;
  1380. pmic_reg_write(p, PFUZE100_SW3AMODE, reg);
  1381. pmic_reg_read(p, PFUZE100_SW3BMODE, &reg);
  1382. reg &= ~(SW_MODE_MASK);
  1383. reg |= PWM_PWM;
  1384. pmic_reg_write(p, PFUZE100_SW3BMODE, reg);
  1385. pmic_reg_read(p, PFUZE100_SW4MODE, &reg);
  1386. reg &= ~(SW_MODE_MASK);
  1387. reg |= PWM_PWM;
  1388. pmic_reg_write(p, PFUZE100_SW4MODE, reg);
  1389. }
  1390. /* configure LTC3676 PMIC */
  1391. else if (!i2c_probe(CONFIG_POWER_LTC3676_I2C_ADDR)) {
  1392. debug("probed LTC3676@0x%x\n", CONFIG_POWER_LTC3676_I2C_ADDR);
  1393. power_ltc3676_init(i2c_pmic);
  1394. p = pmic_get("LTC3676_PMIC");
  1395. if (!p || pmic_probe(p))
  1396. return;
  1397. puts("PMIC: LTC3676\n");
  1398. /*
  1399. * set board-specific scalar for max CPU frequency
  1400. * per CPU based on the LDO enabled Operating Ranges
  1401. * defined in the respective IMX6DQ and IMX6SDL
  1402. * datasheets. The voltage resulting from the R1/R2
  1403. * feedback inputs on Ventana is 1308mV. Note that this
  1404. * is a bit shy of the Vmin of 1350mV in the datasheet
  1405. * for LDO enabled mode but is as high as we can go.
  1406. */
  1407. switch (board) {
  1408. case GW560x:
  1409. /* mask PGOOD during SW3 transition */
  1410. pmic_reg_write(p, LTC3676_DVB3B,
  1411. 0x1f | LTC3676_PGOOD_MASK);
  1412. /* set SW3 (VDD_ARM) */
  1413. pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
  1414. break;
  1415. case GW5903:
  1416. /* mask PGOOD during SW3 transition */
  1417. pmic_reg_write(p, LTC3676_DVB3B,
  1418. 0x1f | LTC3676_PGOOD_MASK);
  1419. /* set SW3 (VDD_ARM) */
  1420. pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
  1421. /* mask PGOOD during SW4 transition */
  1422. pmic_reg_write(p, LTC3676_DVB4B,
  1423. 0x1f | LTC3676_PGOOD_MASK);
  1424. /* set SW4 (VDD_SOC) */
  1425. pmic_reg_write(p, LTC3676_DVB4A, 0x1f);
  1426. break;
  1427. case GW5905:
  1428. /* mask PGOOD during SW1 transition */
  1429. pmic_reg_write(p, LTC3676_DVB1B,
  1430. 0x1f | LTC3676_PGOOD_MASK);
  1431. /* set SW1 (VDD_ARM) */
  1432. pmic_reg_write(p, LTC3676_DVB1A, 0x1f);
  1433. /* mask PGOOD during SW3 transition */
  1434. pmic_reg_write(p, LTC3676_DVB3B,
  1435. 0x1f | LTC3676_PGOOD_MASK);
  1436. /* set SW3 (VDD_SOC) */
  1437. pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
  1438. break;
  1439. default:
  1440. /* mask PGOOD during SW1 transition */
  1441. pmic_reg_write(p, LTC3676_DVB1B,
  1442. 0x1f | LTC3676_PGOOD_MASK);
  1443. /* set SW1 (VDD_SOC) */
  1444. pmic_reg_write(p, LTC3676_DVB1A, 0x1f);
  1445. /* mask PGOOD during SW3 transition */
  1446. pmic_reg_write(p, LTC3676_DVB3B,
  1447. 0x1f | LTC3676_PGOOD_MASK);
  1448. /* set SW3 (VDD_ARM) */
  1449. pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
  1450. }
  1451. /* put all switchers in continuous mode */
  1452. pmic_reg_write(p, LTC3676_BUCK1, 0xc0);
  1453. pmic_reg_write(p, LTC3676_BUCK2, 0xc0);
  1454. pmic_reg_write(p, LTC3676_BUCK3, 0xc0);
  1455. pmic_reg_write(p, LTC3676_BUCK4, 0xc0);
  1456. }
  1457. /* configure MP5416 PMIC */
  1458. else if (!i2c_probe(0x69)) {
  1459. puts("PMIC: MP5416\n");
  1460. switch (board) {
  1461. case GW5910:
  1462. /* SW1: VDD_ARM 1.2V -> (1.275 to 1.475) */
  1463. reg = MP5416_VSET_EN | MP5416_VSET_SW1_SVAL(1475000);
  1464. i2c_write(0x69, MP5416_VSET_SW1, 1, (uint8_t *)&reg, 1);
  1465. /* SW4: VDD_SOC 1.2V -> (1.350 to 1.475) */
  1466. reg = MP5416_VSET_EN | MP5416_VSET_SW4_SVAL(1475000);
  1467. i2c_write(0x69, MP5416_VSET_SW4, 1, (uint8_t *)&reg, 1);
  1468. break;
  1469. }
  1470. }
  1471. }
  1472. #include <fdt_support.h>
  1473. #define WDOG1_ADDR 0x20bc000
  1474. #define WDOG2_ADDR 0x20c0000
  1475. #define GPIO3_ADDR 0x20a4000
  1476. #define USDHC3_ADDR 0x2198000
  1477. static void ft_board_wdog_fixup(void *blob, phys_addr_t addr)
  1478. {
  1479. int off = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt", addr);
  1480. if (off) {
  1481. fdt_delprop(blob, off, "ext-reset-output");
  1482. fdt_delprop(blob, off, "fsl,ext-reset-output");
  1483. }
  1484. }
  1485. void ft_early_fixup(void *blob, int board_type)
  1486. {
  1487. struct ventana_board_info *info = &ventana_info;
  1488. char rev = 0;
  1489. int i;
  1490. /* determine board revision */
  1491. for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
  1492. if (ventana_info.model[i] >= 'A') {
  1493. rev = ventana_info.model[i];
  1494. break;
  1495. }
  1496. }
  1497. /*
  1498. * Board model specific fixups
  1499. */
  1500. switch (board_type) {
  1501. case GW51xx:
  1502. /*
  1503. * disable wdog node for GW51xx-A/B to work around
  1504. * errata causing wdog timer to be unreliable.
  1505. */
  1506. if (rev >= 'A' && rev < 'C') {
  1507. i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt",
  1508. WDOG1_ADDR);
  1509. if (i)
  1510. fdt_status_disabled(blob, i);
  1511. }
  1512. /* GW51xx-E adds WDOG1_B external reset */
  1513. if (rev < 'E')
  1514. ft_board_wdog_fixup(blob, WDOG1_ADDR);
  1515. break;
  1516. case GW52xx:
  1517. /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
  1518. if (info->model[4] == '2') {
  1519. u32 handle = 0;
  1520. u32 *range = NULL;
  1521. i = fdt_node_offset_by_compatible(blob, -1,
  1522. "fsl,imx6q-pcie");
  1523. if (i)
  1524. range = (u32 *)fdt_getprop(blob, i,
  1525. "reset-gpio", NULL);
  1526. if (range) {
  1527. i = fdt_node_offset_by_compat_reg(blob,
  1528. "fsl,imx6q-gpio", GPIO3_ADDR);
  1529. if (i)
  1530. handle = fdt_get_phandle(blob, i);
  1531. if (handle) {
  1532. range[0] = cpu_to_fdt32(handle);
  1533. range[1] = cpu_to_fdt32(23);
  1534. }
  1535. }
  1536. /* these have broken usd_vsel */
  1537. if (strstr((const char *)info->model, "SP318-B") ||
  1538. strstr((const char *)info->model, "SP331-B"))
  1539. gpio_cfg[board_type].usd_vsel = 0;
  1540. /* GW522x-B adds WDOG1_B external reset */
  1541. if (rev < 'B')
  1542. ft_board_wdog_fixup(blob, WDOG1_ADDR);
  1543. }
  1544. /* GW520x-E adds WDOG1_B external reset */
  1545. else if (info->model[4] == '0' && rev < 'E')
  1546. ft_board_wdog_fixup(blob, WDOG1_ADDR);
  1547. break;
  1548. case GW53xx:
  1549. /* GW53xx-E adds WDOG1_B external reset */
  1550. if (rev < 'E')
  1551. ft_board_wdog_fixup(blob, WDOG1_ADDR);
  1552. /* GW53xx-G has an adv7280 instead of an adv7180 */
  1553. else if (rev > 'F') {
  1554. i = fdt_node_offset_by_compatible(blob, -1, "adi,adv7180");
  1555. if (i) {
  1556. fdt_setprop_string(blob, i, "compatible", "adi,adv7280");
  1557. fdt_setprop_empty(blob, i, "adv,force-bt656-4");
  1558. }
  1559. }
  1560. break;
  1561. case GW54xx:
  1562. /*
  1563. * disable serial2 node for GW54xx for compatibility with older
  1564. * 3.10.x kernel that improperly had this node enabled in the DT
  1565. */
  1566. fdt_set_status_by_alias(blob, "serial2", FDT_STATUS_DISABLED,
  1567. 0);
  1568. /* GW54xx-E adds WDOG2_B external reset */
  1569. if (rev < 'E')
  1570. ft_board_wdog_fixup(blob, WDOG2_ADDR);
  1571. /* GW54xx-G has an adv7280 instead of an adv7180 */
  1572. else if (rev > 'F') {
  1573. i = fdt_node_offset_by_compatible(blob, -1, "adi,adv7180");
  1574. if (i) {
  1575. fdt_setprop_string(blob, i, "compatible", "adi,adv7280");
  1576. fdt_setprop_empty(blob, i, "adv,force-bt656-4");
  1577. }
  1578. }
  1579. break;
  1580. case GW551x:
  1581. /* GW551x-C adds WDOG1_B external reset */
  1582. if (rev < 'C')
  1583. ft_board_wdog_fixup(blob, WDOG1_ADDR);
  1584. break;
  1585. case GW5901:
  1586. case GW5902:
  1587. /* GW5901/GW5901 revB adds WDOG1_B as an external reset */
  1588. if (rev < 'B')
  1589. ft_board_wdog_fixup(blob, WDOG1_ADDR);
  1590. break;
  1591. }
  1592. /* remove no-1-8-v if UHS-I support is present */
  1593. if (gpio_cfg[board_type].usd_vsel) {
  1594. debug("Enabling UHS-I support\n");
  1595. i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-usdhc",
  1596. USDHC3_ADDR);
  1597. if (i)
  1598. fdt_delprop(blob, i, "no-1-8-v");
  1599. }
  1600. }
  1601. #ifdef CONFIG_FSL_ESDHC_IMX
  1602. static struct fsl_esdhc_cfg usdhc_cfg[2];
  1603. int board_mmc_init(struct bd_info *bis)
  1604. {
  1605. struct ventana_board_info ventana_info;
  1606. int board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
  1607. int ret;
  1608. switch (board_type) {
  1609. case GW52xx:
  1610. case GW53xx:
  1611. case GW54xx:
  1612. case GW553x:
  1613. case GW5910:
  1614. case GW5912:
  1615. /* usdhc3: 4bit microSD */
  1616. SETUP_IOMUX_PADS(usdhc3_pads);
  1617. usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
  1618. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  1619. usdhc_cfg[0].max_bus_width = 4;
  1620. return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  1621. case GW560x:
  1622. /* usdhc2: 8-bit eMMC */
  1623. SETUP_IOMUX_PADS(gw560x_emmc_sd2_pads);
  1624. usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
  1625. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  1626. usdhc_cfg[0].max_bus_width = 8;
  1627. ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  1628. if (ret)
  1629. return ret;
  1630. /* usdhc3: 4-bit microSD */
  1631. SETUP_IOMUX_PADS(usdhc3_pads);
  1632. usdhc_cfg[1].esdhc_base = USDHC3_BASE_ADDR;
  1633. usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  1634. usdhc_cfg[1].max_bus_width = 4;
  1635. return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
  1636. case GW5903:
  1637. /* usdhc3: 8-bit eMMC */
  1638. SETUP_IOMUX_PADS(gw5904_emmc_pads);
  1639. usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
  1640. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  1641. usdhc_cfg[0].max_bus_width = 8;
  1642. ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  1643. if (ret)
  1644. return ret;
  1645. /* usdhc2: 4-bit microSD */
  1646. SETUP_IOMUX_PADS(gw5904_mmc_pads);
  1647. usdhc_cfg[1].esdhc_base = USDHC2_BASE_ADDR;
  1648. usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  1649. usdhc_cfg[1].max_bus_width = 4;
  1650. return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
  1651. case GW5904:
  1652. case GW5905:
  1653. case GW5909:
  1654. /* usdhc3: 8bit eMMC */
  1655. SETUP_IOMUX_PADS(gw5904_emmc_pads);
  1656. usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
  1657. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  1658. usdhc_cfg[0].max_bus_width = 8;
  1659. return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  1660. default:
  1661. /* doesn't have MMC */
  1662. printf("None");
  1663. return -1;
  1664. }
  1665. }
  1666. int board_mmc_getcd(struct mmc *mmc)
  1667. {
  1668. struct ventana_board_info ventana_info;
  1669. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  1670. int board = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
  1671. int gpio = gpio_cfg[board].mmc_cd;
  1672. /* Card Detect */
  1673. switch (board) {
  1674. case GW560x:
  1675. /* emmc is always present */
  1676. if (cfg->esdhc_base == USDHC2_BASE_ADDR)
  1677. return 1;
  1678. break;
  1679. case GW5903:
  1680. case GW5904:
  1681. case GW5905:
  1682. case GW5909:
  1683. /* emmc is always present */
  1684. if (cfg->esdhc_base == USDHC3_BASE_ADDR)
  1685. return 1;
  1686. break;
  1687. }
  1688. if (gpio) {
  1689. debug("%s: gpio%d=%d\n", __func__, gpio, gpio_get_value(gpio));
  1690. return !gpio_get_value(gpio);
  1691. }
  1692. return -1;
  1693. }
  1694. #endif /* CONFIG_FSL_ESDHC_IMX */