spl.c 4.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Atmel Corporation
  4. * Copyright (C) 2019 Stefan Roese <sr@denx.de>
  5. */
  6. #include <common.h>
  7. #include <nand.h>
  8. #include <spl.h>
  9. #include <asm/arch/at91sam9x5_matrix.h>
  10. #include <asm/arch/at91sam9_smc.h>
  11. #include <asm/arch/atmel_mpddrc.h>
  12. #include <asm/arch/clk.h>
  13. #include <asm/arch/gpio.h>
  14. static void at91sam9x5ek_nand_hw_init(void)
  15. {
  16. struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  17. struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  18. unsigned long csa;
  19. /* Enable CS3 */
  20. csa = readl(&matrix->ebicsa);
  21. csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
  22. /* NAND flash on D16 */
  23. csa |= AT91_MATRIX_NFD0_ON_D16;
  24. /* Configure IO drive */
  25. csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
  26. writel(csa, &matrix->ebicsa);
  27. /* Configure SMC CS3 for NAND/SmartMedia */
  28. writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  29. AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  30. &smc->cs[3].setup);
  31. writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
  32. AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
  33. &smc->cs[3].pulse);
  34. writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6),
  35. &smc->cs[3].cycle);
  36. writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  37. AT91_SMC_MODE_EXNW_DISABLE |
  38. #ifdef CONFIG_SYS_NAND_DBW_16
  39. AT91_SMC_MODE_DBW_16 |
  40. #else /* CONFIG_SYS_NAND_DBW_8 */
  41. AT91_SMC_MODE_DBW_8 |
  42. #endif
  43. AT91_SMC_MODE_TDF_CYCLE(1),
  44. &smc->cs[3].mode);
  45. at91_periph_clk_enable(ATMEL_ID_PIOCD);
  46. /* Configure RDY/BSY */
  47. at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  48. /* Enable NandFlash */
  49. at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  50. at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
  51. at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
  52. at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */
  53. at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */
  54. at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1);
  55. at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1);
  56. at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1);
  57. at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1);
  58. at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1);
  59. at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1);
  60. at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1);
  61. at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1);
  62. }
  63. void at91_spl_board_init(void)
  64. {
  65. at91sam9x5ek_nand_hw_init();
  66. }
  67. static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
  68. {
  69. ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
  70. ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
  71. ATMEL_MPDDRC_CR_NR_ROW_13 |
  72. ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
  73. ATMEL_MPDDRC_CR_NB_8BANKS |
  74. ATMEL_MPDDRC_CR_DECOD_INTERLEAVED);
  75. ddr2->rtr = 0x411;
  76. ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
  77. 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
  78. 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
  79. 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
  80. 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
  81. 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
  82. 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
  83. 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
  84. ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
  85. 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
  86. 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
  87. 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
  88. ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
  89. 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
  90. 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
  91. 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
  92. 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
  93. }
  94. void mem_init(void)
  95. {
  96. struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  97. struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  98. struct atmel_mpddrc_config ddr2;
  99. unsigned long csa;
  100. ddr2_conf(&ddr2);
  101. /* Enable DDR2 clock */
  102. writel(AT91_PMC_DDR, &pmc->scer);
  103. /* Chip select 1 is for DDR2/SDRAM */
  104. csa = readl(&matrix->ebicsa);
  105. csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
  106. csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
  107. csa |= AT91_MATRIX_EBI_DBPD_OFF;
  108. csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
  109. writel(csa, &matrix->ebicsa);
  110. /* DDRAM2 Controller initialize */
  111. ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);
  112. }