tlb.c 4.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <asm/mmu.h>
  7. struct fsl_e_tlb_entry tlb_table[] = {
  8. /* TLB 0 - for temp stack in cache */
  9. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
  10. CONFIG_SYS_INIT_RAM_ADDR_PHYS,
  11. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  12. 0, 0, BOOKE_PAGESZ_4K, 0),
  13. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  14. CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
  15. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  16. 0, 0, BOOKE_PAGESZ_4K, 0),
  17. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  18. CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
  19. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  20. 0, 0, BOOKE_PAGESZ_4K, 0),
  21. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  22. CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
  23. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  24. 0, 0, BOOKE_PAGESZ_4K, 0),
  25. /* TLB 1 */
  26. /* *I*** - Covers boot page */
  27. #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
  28. /*
  29. * *I*G - L3SRAM. When L3 is used as 512K SRAM */
  30. SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
  31. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  32. 0, 0, BOOKE_PAGESZ_512K, 1),
  33. #else
  34. SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
  35. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  36. 0, 0, BOOKE_PAGESZ_4K, 1),
  37. #endif
  38. /* *I*G* - CCSRBAR */
  39. SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  40. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  41. 0, 1, BOOKE_PAGESZ_16M, 1),
  42. /* *I*G* - Flash, localbus */
  43. /* This will be changed to *I*G* after relocation to RAM. */
  44. SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
  45. MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
  46. 0, 2, BOOKE_PAGESZ_256M, 1),
  47. #ifndef CONFIG_SPL_BUILD
  48. /* *I*G* - PCI */
  49. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
  50. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  51. 0, 3, BOOKE_PAGESZ_1G, 1),
  52. /* *I*G* - PCI */
  53. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
  54. CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
  55. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  56. 0, 4, BOOKE_PAGESZ_256M, 1),
  57. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
  58. CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
  59. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  60. 0, 5, BOOKE_PAGESZ_256M, 1),
  61. /* *I*G* - PCI I/O */
  62. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
  63. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  64. 0, 6, BOOKE_PAGESZ_256K, 1),
  65. /* Bman/Qman */
  66. #ifdef CONFIG_SYS_BMAN_MEM_PHYS
  67. SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
  68. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  69. 0, 9, BOOKE_PAGESZ_16M, 1),
  70. SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
  71. CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
  72. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  73. 0, 10, BOOKE_PAGESZ_16M, 1),
  74. #endif
  75. #ifdef CONFIG_SYS_QMAN_MEM_PHYS
  76. SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
  77. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  78. 0, 11, BOOKE_PAGESZ_16M, 1),
  79. SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
  80. CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
  81. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  82. 0, 12, BOOKE_PAGESZ_16M, 1),
  83. #endif
  84. #endif
  85. #ifdef CONFIG_SYS_DCSRBAR_PHYS
  86. SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
  87. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  88. 0, 13, BOOKE_PAGESZ_32M, 1),
  89. #endif
  90. #ifdef CONFIG_SYS_NAND_BASE
  91. /*
  92. * *I*G - NAND
  93. * entry 14 and 15 has been used hard coded, they will be disabled
  94. * in cpu_init_f, so we use entry 16 for nand.
  95. */
  96. SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
  97. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  98. 0, 16, BOOKE_PAGESZ_64K, 1),
  99. #endif
  100. #ifdef CONFIG_SYS_CPLD_BASE
  101. SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
  102. MAS3_SW|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  103. 0, 17, BOOKE_PAGESZ_4K, 1),
  104. #endif
  105. #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
  106. SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
  107. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
  108. 0, 18, BOOKE_PAGESZ_2G, 1)
  109. #endif
  110. };
  111. int num_tlb_entries = ARRAY_SIZE(tlb_table);