eth.c 4.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. *
  5. * Chunhe Lan <Chunhe.Lan@freescale.com>
  6. */
  7. #include <common.h>
  8. #include <command.h>
  9. #include <fdt_support.h>
  10. #include <net.h>
  11. #include <netdev.h>
  12. #include <asm/mmu.h>
  13. #include <asm/processor.h>
  14. #include <asm/cache.h>
  15. #include <asm/immap_85xx.h>
  16. #include <asm/fsl_law.h>
  17. #include <fsl_ddr_sdram.h>
  18. #include <asm/fsl_serdes.h>
  19. #include <asm/fsl_portals.h>
  20. #include <asm/fsl_liodn.h>
  21. #include <malloc.h>
  22. #include <fm_eth.h>
  23. #include <fsl_mdio.h>
  24. #include <miiphy.h>
  25. #include <phy.h>
  26. #include <fsl_dtsec.h>
  27. #include <asm/fsl_serdes.h>
  28. #include <hwconfig.h>
  29. #include "../common/fman.h"
  30. #include "t4rdb.h"
  31. void fdt_fixup_board_enet(void *fdt)
  32. {
  33. return;
  34. }
  35. int board_eth_init(struct bd_info *bis)
  36. {
  37. #if defined(CONFIG_FMAN_ENET)
  38. int i, interface;
  39. struct memac_mdio_info dtsec_mdio_info;
  40. struct memac_mdio_info tgec_mdio_info;
  41. struct mii_dev *dev;
  42. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  43. u32 srds_prtcl_s1, srds_prtcl_s2;
  44. srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
  45. FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  46. srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  47. srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
  48. FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
  49. srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
  50. dtsec_mdio_info.regs =
  51. (struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;
  52. dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
  53. /* Register the 1G MDIO bus */
  54. fm_memac_mdio_init(bis, &dtsec_mdio_info);
  55. tgec_mdio_info.regs =
  56. (struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
  57. tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
  58. /* Register the 10G MDIO bus */
  59. fm_memac_mdio_init(bis, &tgec_mdio_info);
  60. if ((srds_prtcl_s1 == 28) || (srds_prtcl_s1 == 27)) {
  61. /* SGMII */
  62. fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1);
  63. fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2);
  64. fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY_ADDR3);
  65. fm_info_set_phy_address(FM1_DTSEC4, SGMII_PHY_ADDR4);
  66. } else {
  67. puts("Invalid SerDes1 protocol for T4240RDB\n");
  68. }
  69. fm_disable_port(FM1_DTSEC5);
  70. fm_disable_port(FM1_DTSEC6);
  71. for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
  72. interface = fm_info_get_enet_if(i);
  73. switch (interface) {
  74. case PHY_INTERFACE_MODE_SGMII:
  75. dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
  76. fm_info_set_mdio(i, dev);
  77. break;
  78. default:
  79. break;
  80. }
  81. }
  82. for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
  83. switch (fm_info_get_enet_if(i)) {
  84. case PHY_INTERFACE_MODE_XGMII:
  85. dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
  86. fm_info_set_mdio(i, dev);
  87. break;
  88. default:
  89. break;
  90. }
  91. }
  92. #if (CONFIG_SYS_NUM_FMAN == 2)
  93. if ((srds_prtcl_s2 == 56) || (srds_prtcl_s2 == 55)) {
  94. /* SGMII && XFI */
  95. fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5);
  96. fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6);
  97. fm_info_set_phy_address(FM2_DTSEC3, SGMII_PHY_ADDR7);
  98. fm_info_set_phy_address(FM2_DTSEC4, SGMII_PHY_ADDR8);
  99. fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
  100. fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
  101. fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC2_PHY_ADDR);
  102. fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC1_PHY_ADDR);
  103. } else {
  104. puts("Invalid SerDes2 protocol for T4240RDB\n");
  105. }
  106. fm_disable_port(FM2_DTSEC5);
  107. fm_disable_port(FM2_DTSEC6);
  108. for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
  109. interface = fm_info_get_enet_if(i);
  110. switch (interface) {
  111. case PHY_INTERFACE_MODE_SGMII:
  112. dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
  113. fm_info_set_mdio(i, dev);
  114. break;
  115. default:
  116. break;
  117. }
  118. }
  119. for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
  120. switch (fm_info_get_enet_if(i)) {
  121. case PHY_INTERFACE_MODE_XGMII:
  122. dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
  123. fm_info_set_mdio(i, dev);
  124. break;
  125. default:
  126. break;
  127. }
  128. }
  129. #endif /* CONFIG_SYS_NUM_FMAN */
  130. cpu_eth_init(bis);
  131. #endif /* CONFIG_FMAN_ENET */
  132. return pci_eth_init(bis);
  133. }