ddr.h 2.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef __DDR_H__
  6. #define __DDR_H__
  7. struct board_specific_parameters {
  8. u32 n_ranks;
  9. u32 datarate_mhz_high;
  10. u32 rank_gb;
  11. u32 clk_adjust;
  12. u32 wrlvl_start;
  13. u32 wrlvl_ctl_2;
  14. u32 wrlvl_ctl_3;
  15. };
  16. /*
  17. * These tables contain all valid speeds we want to override with board
  18. * specific parameters. datarate_mhz_high values need to be in ascending order
  19. * for each n_ranks group.
  20. */
  21. static const struct board_specific_parameters udimm0[] = {
  22. /*
  23. * memory controller 0
  24. * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
  25. * ranks| mhz| GB |adjst| start | ctl2 | ctl3
  26. */
  27. {2, 1350, 4, 8, 8, 0x0809090b, 0x0c0c0d0a},
  28. {2, 1350, 0, 10, 7, 0x0709090b, 0x0c0c0d09},
  29. {2, 1666, 4, 8, 8, 0x080a0a0d, 0x0d10100b},
  30. {2, 1666, 0, 10, 7, 0x080a0a0c, 0x0d0d0e0a},
  31. {2, 1900, 0, 8, 8, 0x090a0b0e, 0x0f11120c},
  32. {2, 2140, 0, 8, 8, 0x090a0b0e, 0x0f11120c},
  33. {1, 1350, 0, 10, 8, 0x0809090b, 0x0c0c0d0a},
  34. {1, 1700, 0, 10, 8, 0x080a0a0c, 0x0c0d0e0a},
  35. {1, 1900, 0, 8, 8, 0x080a0a0c, 0x0e0e0f0a},
  36. {1, 2140, 0, 8, 8, 0x090a0b0c, 0x0e0f100b},
  37. {}
  38. };
  39. static const struct board_specific_parameters rdimm0[] = {
  40. /*
  41. * memory controller 0
  42. * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
  43. * ranks| mhz| GB |adjst| start | ctl2 | ctl3
  44. */
  45. {4, 1350, 0, 10, 9, 0x08070605, 0x06070806},
  46. {4, 1666, 0, 10, 11, 0x0a080706, 0x07090906},
  47. {4, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07},
  48. {2, 1350, 0, 10, 9, 0x08070605, 0x06070806},
  49. {2, 1666, 0, 10, 11, 0x0a090806, 0x08090a06},
  50. {2, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07},
  51. {1, 1350, 0, 10, 9, 0x08070605, 0x06070806},
  52. {1, 1666, 0, 10, 11, 0x0a090806, 0x08090a06},
  53. {1, 2140, 0, 8, 12, 0x0b090807, 0x080a0b07},
  54. {}
  55. };
  56. /*
  57. * The three slots have slightly different timing. The center values are good
  58. * for all slots. We use identical speed tables for them. In future use, if
  59. * DIMMs require separated tables, make more entries as needed.
  60. */
  61. static const struct board_specific_parameters *udimms[] = {
  62. udimm0,
  63. };
  64. /*
  65. * The three slots have slightly different timing. See comments above.
  66. */
  67. static const struct board_specific_parameters *rdimms[] = {
  68. rdimm0,
  69. };
  70. #endif