ddr.c 3.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <i2c.h>
  7. #include <hwconfig.h>
  8. #include <init.h>
  9. #include <log.h>
  10. #include <asm/global_data.h>
  11. #include <asm/mmu.h>
  12. #include <fsl_ddr_sdram.h>
  13. #include <fsl_ddr_dimm_params.h>
  14. #include <asm/fsl_law.h>
  15. #include "ddr.h"
  16. DECLARE_GLOBAL_DATA_PTR;
  17. void fsl_ddr_board_options(memctl_options_t *popts,
  18. dimm_params_t *pdimm,
  19. unsigned int ctrl_num)
  20. {
  21. const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  22. ulong ddr_freq;
  23. if (ctrl_num > 2) {
  24. printf("Not supported controller number %d\n", ctrl_num);
  25. return;
  26. }
  27. if (!pdimm->n_ranks)
  28. return;
  29. /*
  30. * we use identical timing for all slots. If needed, change the code
  31. * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
  32. */
  33. if (popts->registered_dimm_en)
  34. pbsp = rdimms[0];
  35. else
  36. pbsp = udimms[0];
  37. /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
  38. * freqency and n_banks specified in board_specific_parameters table.
  39. */
  40. ddr_freq = get_ddr_freq(0) / 1000000;
  41. while (pbsp->datarate_mhz_high) {
  42. if (pbsp->n_ranks == pdimm->n_ranks &&
  43. (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
  44. if (ddr_freq <= pbsp->datarate_mhz_high) {
  45. popts->clk_adjust = pbsp->clk_adjust;
  46. popts->wrlvl_start = pbsp->wrlvl_start;
  47. popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  48. popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  49. goto found;
  50. }
  51. pbsp_highest = pbsp;
  52. }
  53. pbsp++;
  54. }
  55. if (pbsp_highest) {
  56. printf("Error: board specific timing not found for data\n"
  57. "rate %lu MT/s\n"
  58. "Trying to use the highest speed (%u) parameters\n",
  59. ddr_freq, pbsp_highest->datarate_mhz_high);
  60. popts->clk_adjust = pbsp_highest->clk_adjust;
  61. popts->wrlvl_start = pbsp_highest->wrlvl_start;
  62. popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  63. popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  64. } else {
  65. panic("DIMM is not supported by this board");
  66. }
  67. found:
  68. debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
  69. "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x,\n"
  70. "wrlvl_ctrl_3 0x%x\n",
  71. pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
  72. pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
  73. pbsp->wrlvl_ctl_3);
  74. /*
  75. * Factors to consider for half-strength driver enable:
  76. * - number of DIMMs installed
  77. */
  78. popts->half_strength_driver_enable = 0;
  79. /*
  80. * Write leveling override
  81. */
  82. popts->wrlvl_override = 1;
  83. popts->wrlvl_sample = 0xf;
  84. /*
  85. * Rtt and Rtt_WR override
  86. */
  87. popts->rtt_override = 0;
  88. /* Enable ZQ calibration */
  89. popts->zq_en = 1;
  90. /* DHC_EN =1, ODT = 75 Ohm */
  91. popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
  92. popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
  93. /* optimize cpo for erratum A-009942 */
  94. popts->cpo_sample = 0x64;
  95. }
  96. int dram_init(void)
  97. {
  98. phys_size_t dram_size;
  99. puts("Initializing....using SPD\n");
  100. #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
  101. dram_size = fsl_ddr_sdram();
  102. #else
  103. /* DDR has been initialised by first stage boot loader */
  104. dram_size = fsl_ddr_sdram_size();
  105. #endif
  106. dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  107. dram_size *= 0x100000;
  108. gd->ram_size = dram_size;
  109. return 0;
  110. }