t102xrdb.c 8.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. * Copyright 2020 NXP
  5. */
  6. #include <common.h>
  7. #include <command.h>
  8. #include <env.h>
  9. #include <fdt_support.h>
  10. #include <i2c.h>
  11. #include <image.h>
  12. #include <init.h>
  13. #include <netdev.h>
  14. #include <asm/global_data.h>
  15. #include <linux/compiler.h>
  16. #include <asm/mmu.h>
  17. #include <asm/processor.h>
  18. #include <asm/immap_85xx.h>
  19. #include <asm/fsl_law.h>
  20. #include <asm/fsl_serdes.h>
  21. #include <asm/fsl_liodn.h>
  22. #include <fm_eth.h>
  23. #include "t102xrdb.h"
  24. #ifdef CONFIG_TARGET_T1024RDB
  25. #include "cpld.h"
  26. #elif defined(CONFIG_TARGET_T1023RDB)
  27. #include <i2c.h>
  28. #include <mmc.h>
  29. #endif
  30. #include "../common/sleep.h"
  31. DECLARE_GLOBAL_DATA_PTR;
  32. #ifdef CONFIG_TARGET_T1023RDB
  33. enum {
  34. GPIO1_SD_SEL = 0x00020000, /* GPIO1_14, 0: eMMC, 1:SD/MMC */
  35. GPIO1_EMMC_SEL,
  36. GPIO3_GET_VERSION, /* GPIO3_4/5, 00:RevB, 01: RevC */
  37. GPIO3_BRD_VER_MASK = 0x0c000000,
  38. GPIO3_OFFSET = 0x2000,
  39. I2C_GET_BANK,
  40. I2C_SET_BANK0,
  41. I2C_SET_BANK4,
  42. };
  43. #endif
  44. int checkboard(void)
  45. {
  46. struct cpu_type *cpu = gd->arch.cpu;
  47. static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
  48. ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  49. u32 srds_s1;
  50. srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  51. srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  52. printf("Board: %sRDB, ", cpu->name);
  53. #if defined(CONFIG_TARGET_T1024RDB)
  54. printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
  55. CPLD_READ(hw_ver), CPLD_READ(sw_ver));
  56. #elif defined(CONFIG_TARGET_T1023RDB)
  57. printf("Rev%c, ", t1023rdb_ctrl(GPIO3_GET_VERSION) + 'B');
  58. #endif
  59. printf("boot from ");
  60. #ifdef CONFIG_SDCARD
  61. puts("SD/MMC\n");
  62. #elif CONFIG_SPIFLASH
  63. puts("SPI\n");
  64. #elif defined(CONFIG_TARGET_T1024RDB)
  65. u8 reg;
  66. reg = CPLD_READ(flash_csr);
  67. if (reg & CPLD_BOOT_SEL) {
  68. puts("NAND\n");
  69. } else {
  70. reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
  71. printf("NOR vBank%d\n", reg);
  72. }
  73. #elif defined(CONFIG_TARGET_T1023RDB)
  74. #ifdef CONFIG_MTD_RAW_NAND
  75. puts("NAND\n");
  76. #else
  77. printf("NOR vBank%d\n", t1023rdb_ctrl(I2C_GET_BANK));
  78. #endif
  79. #endif
  80. puts("SERDES Reference Clocks:\n");
  81. if (srds_s1 == 0x95)
  82. printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
  83. else
  84. printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[1]);
  85. return 0;
  86. }
  87. #ifdef CONFIG_TARGET_T1024RDB
  88. static void board_mux_lane(void)
  89. {
  90. ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  91. u32 srds_prtcl_s1;
  92. u8 reg = CPLD_READ(misc_ctl_status);
  93. srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
  94. FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  95. srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  96. if (srds_prtcl_s1 == 0x95) {
  97. /* Route Lane B to PCIE */
  98. CPLD_WRITE(misc_ctl_status, reg & ~CPLD_PCIE_SGMII_MUX);
  99. } else {
  100. /* Route Lane B to SGMII */
  101. CPLD_WRITE(misc_ctl_status, reg | CPLD_PCIE_SGMII_MUX);
  102. }
  103. CPLD_WRITE(boot_override, CPLD_OVERRIDE_MUX_EN);
  104. }
  105. #endif
  106. int board_early_init_f(void)
  107. {
  108. #if defined(CONFIG_DEEP_SLEEP)
  109. if (is_warm_boot())
  110. fsl_dp_disable_console();
  111. #endif
  112. return 0;
  113. }
  114. int board_early_init_r(void)
  115. {
  116. #ifdef CONFIG_SYS_FLASH_BASE
  117. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  118. int flash_esel = find_tlb_idx((void *)flashbase, 1);
  119. /*
  120. * Remap Boot flash region to caching-inhibited
  121. * so that flash can be erased properly.
  122. */
  123. /* Flush d-cache and invalidate i-cache of any FLASH data */
  124. flush_dcache();
  125. invalidate_icache();
  126. if (flash_esel == -1) {
  127. /* very unlikely unless something is messed up */
  128. puts("Error: Could not find TLB for FLASH BASE\n");
  129. flash_esel = 2; /* give our best effort to continue */
  130. } else {
  131. /* invalidate existing TLB entry for flash + promjet */
  132. disable_tlb(flash_esel);
  133. }
  134. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
  135. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  136. 0, flash_esel, BOOKE_PAGESZ_256M, 1);
  137. #endif
  138. #ifdef CONFIG_TARGET_T1024RDB
  139. board_mux_lane();
  140. #endif
  141. return 0;
  142. }
  143. unsigned long get_board_sys_clk(void)
  144. {
  145. return CONFIG_SYS_CLK_FREQ;
  146. }
  147. unsigned long get_board_ddr_clk(void)
  148. {
  149. return CONFIG_DDR_CLK_FREQ;
  150. }
  151. #ifdef CONFIG_TARGET_T1024RDB
  152. void board_reset(void)
  153. {
  154. CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
  155. }
  156. #endif
  157. int misc_init_r(void)
  158. {
  159. return 0;
  160. }
  161. int ft_board_setup(void *blob, struct bd_info *bd)
  162. {
  163. phys_addr_t base;
  164. phys_size_t size;
  165. ft_cpu_setup(blob, bd);
  166. base = env_get_bootm_low();
  167. size = env_get_bootm_size();
  168. fdt_fixup_memory(blob, (u64)base, (u64)size);
  169. #ifdef CONFIG_PCI
  170. pci_of_setup(blob, bd);
  171. #endif
  172. fdt_fixup_liodn(blob);
  173. fsl_fdt_fixup_dr_usb(blob, bd);
  174. #ifdef CONFIG_SYS_DPAA_FMAN
  175. #ifndef CONFIG_DM_ETH
  176. fdt_fixup_fman_ethernet(blob);
  177. #endif
  178. fdt_fixup_board_enet(blob);
  179. #endif
  180. #ifdef CONFIG_TARGET_T1023RDB
  181. if (t1023rdb_ctrl(GPIO3_GET_VERSION) > 0)
  182. fdt_enable_nor(blob);
  183. #endif
  184. return 0;
  185. }
  186. #ifdef CONFIG_TARGET_T1023RDB
  187. /* Enable NOR flash for RevC */
  188. static void fdt_enable_nor(void *blob)
  189. {
  190. int nodeoff = fdt_node_offset_by_compatible(blob, 0, "cfi-flash");
  191. if (nodeoff >= 0)
  192. fdt_status_okay(blob, nodeoff);
  193. else
  194. printf("WARNING unable to set status for NOR\n");
  195. }
  196. int board_mmc_getcd(struct mmc *mmc)
  197. {
  198. ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
  199. u32 val = in_be32(&pgpio->gpdat);
  200. /* GPIO1_14, 0: eMMC, 1: SD/MMC */
  201. val &= GPIO1_SD_SEL;
  202. return val ? -1 : 1;
  203. }
  204. int board_mmc_getwp(struct mmc *mmc)
  205. {
  206. ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
  207. u32 val = in_be32(&pgpio->gpdat);
  208. val &= GPIO1_SD_SEL;
  209. return val ? -1 : 0;
  210. }
  211. static u32 t1023rdb_ctrl(u32 ctrl_type)
  212. {
  213. ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
  214. ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  215. u32 val;
  216. u8 tmp;
  217. int bus_num = I2C_PCA6408_BUS_NUM;
  218. #if CONFIG_IS_ENABLED(DM_I2C)
  219. struct udevice *dev;
  220. int ret;
  221. ret = i2c_get_chip_for_busnum(bus_num, I2C_PCA6408_ADDR,
  222. 1, &dev);
  223. if (ret) {
  224. printf("%s: Cannot find udev for a bus %d\n", __func__,
  225. bus_num);
  226. return ret;
  227. }
  228. switch (ctrl_type) {
  229. case GPIO1_SD_SEL:
  230. val = in_be32(&pgpio->gpdat);
  231. val |= GPIO1_SD_SEL;
  232. out_be32(&pgpio->gpdat, val);
  233. setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
  234. break;
  235. case GPIO1_EMMC_SEL:
  236. val = in_be32(&pgpio->gpdat);
  237. val &= ~GPIO1_SD_SEL;
  238. out_be32(&pgpio->gpdat, val);
  239. setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
  240. break;
  241. case GPIO3_GET_VERSION:
  242. pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR
  243. + GPIO3_OFFSET);
  244. val = in_be32(&pgpio->gpdat);
  245. val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3;
  246. if (val == 0x3) /* GPIO3_4/5 not used on RevB */
  247. val = 0;
  248. return val;
  249. case I2C_GET_BANK:
  250. dm_i2c_read(dev, 0, &tmp, 1);
  251. tmp &= 0x7;
  252. tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2);
  253. return tmp;
  254. case I2C_SET_BANK0:
  255. tmp = 0x0;
  256. dm_i2c_write(dev, 1, &tmp, 1);
  257. tmp = 0xf8;
  258. dm_i2c_write(dev, 3, &tmp, 1);
  259. /* asserting HRESET_REQ */
  260. out_be32(&gur->rstcr, 0x2);
  261. break;
  262. case I2C_SET_BANK4:
  263. tmp = 0x1;
  264. dm_i2c_write(dev, 1, &tmp, 1);
  265. tmp = 0xf8;
  266. dm_i2c_write(dev, 3, &tmp, 1);
  267. out_be32(&gur->rstcr, 0x2);
  268. break;
  269. default:
  270. break;
  271. }
  272. #else
  273. u32 orig_bus;
  274. orig_bus = i2c_get_bus_num();
  275. switch (ctrl_type) {
  276. case GPIO1_SD_SEL:
  277. val = in_be32(&pgpio->gpdat);
  278. val |= GPIO1_SD_SEL;
  279. out_be32(&pgpio->gpdat, val);
  280. setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
  281. break;
  282. case GPIO1_EMMC_SEL:
  283. val = in_be32(&pgpio->gpdat);
  284. val &= ~GPIO1_SD_SEL;
  285. out_be32(&pgpio->gpdat, val);
  286. setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
  287. break;
  288. case GPIO3_GET_VERSION:
  289. pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR
  290. + GPIO3_OFFSET);
  291. val = in_be32(&pgpio->gpdat);
  292. val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3;
  293. if (val == 0x3) /* GPIO3_4/5 not used on RevB */
  294. val = 0;
  295. return val;
  296. case I2C_GET_BANK:
  297. i2c_set_bus_num(bus_num);
  298. i2c_read(I2C_PCA6408_ADDR, 0, 1, &tmp, 1);
  299. tmp &= 0x7;
  300. tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2);
  301. i2c_set_bus_num(orig_bus);
  302. return tmp;
  303. case I2C_SET_BANK0:
  304. i2c_set_bus_num(bus_num);
  305. tmp = 0x0;
  306. i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
  307. tmp = 0xf8;
  308. i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
  309. /* asserting HRESET_REQ */
  310. out_be32(&gur->rstcr, 0x2);
  311. break;
  312. case I2C_SET_BANK4:
  313. i2c_set_bus_num(bus_num);
  314. tmp = 0x1;
  315. i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
  316. tmp = 0xf8;
  317. i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
  318. out_be32(&gur->rstcr, 0x2);
  319. break;
  320. default:
  321. break;
  322. }
  323. #endif
  324. return 0;
  325. }
  326. static int switch_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
  327. char *const argv[])
  328. {
  329. if (argc < 2)
  330. return CMD_RET_USAGE;
  331. if (!strcmp(argv[1], "bank0"))
  332. t1023rdb_ctrl(I2C_SET_BANK0);
  333. else if (!strcmp(argv[1], "bank4") || !strcmp(argv[1], "altbank"))
  334. t1023rdb_ctrl(I2C_SET_BANK4);
  335. else if (!strcmp(argv[1], "sd"))
  336. t1023rdb_ctrl(GPIO1_SD_SEL);
  337. else if (!strcmp(argv[1], "emmc"))
  338. t1023rdb_ctrl(GPIO1_EMMC_SEL);
  339. else
  340. return CMD_RET_USAGE;
  341. return 0;
  342. }
  343. U_BOOT_CMD(
  344. switch, 2, 0, switch_cmd,
  345. "for bank0/bank4/sd/emmc switch control in runtime",
  346. "command (e.g. switch bank4)"
  347. );
  348. #endif