ddr.c 6.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <i2c.h>
  7. #include <hwconfig.h>
  8. #include <init.h>
  9. #include <log.h>
  10. #include <asm/global_data.h>
  11. #include <asm/mmu.h>
  12. #include <fsl_ddr_sdram.h>
  13. #include <fsl_ddr_dimm_params.h>
  14. #include <asm/fsl_law.h>
  15. #include <asm/mpc85xx_gpio.h>
  16. #include <linux/delay.h>
  17. DECLARE_GLOBAL_DATA_PTR;
  18. struct board_specific_parameters {
  19. u32 n_ranks;
  20. u32 datarate_mhz_high;
  21. u32 rank_gb;
  22. u32 clk_adjust;
  23. u32 wrlvl_start;
  24. u32 wrlvl_ctl_2;
  25. u32 wrlvl_ctl_3;
  26. };
  27. /*
  28. * datarate_mhz_high values need to be in ascending order
  29. */
  30. static const struct board_specific_parameters udimm0[] = {
  31. /*
  32. * memory controller 0
  33. * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
  34. * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
  35. */
  36. {2, 833, 0, 8, 6, 0x06060607, 0x08080807,},
  37. {2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
  38. {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
  39. {1, 833, 0, 8, 6, 0x06060607, 0x08080807,},
  40. {1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
  41. {1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
  42. {}
  43. };
  44. static const struct board_specific_parameters *udimms[] = {
  45. udimm0,
  46. };
  47. void fsl_ddr_board_options(memctl_options_t *popts,
  48. dimm_params_t *pdimm,
  49. unsigned int ctrl_num)
  50. {
  51. const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  52. ulong ddr_freq;
  53. struct cpu_type *cpu = gd->arch.cpu;
  54. if (ctrl_num > 1) {
  55. printf("Not supported controller number %d\n", ctrl_num);
  56. return;
  57. }
  58. if (!pdimm->n_ranks)
  59. return;
  60. pbsp = udimms[0];
  61. /* Get clk_adjust according to the board ddr freqency and n_banks
  62. * specified in board_specific_parameters table.
  63. */
  64. ddr_freq = get_ddr_freq(0) / 1000000;
  65. while (pbsp->datarate_mhz_high) {
  66. if (pbsp->n_ranks == pdimm->n_ranks &&
  67. (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
  68. if (ddr_freq <= pbsp->datarate_mhz_high) {
  69. popts->clk_adjust = pbsp->clk_adjust;
  70. popts->wrlvl_start = pbsp->wrlvl_start;
  71. popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  72. popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  73. goto found;
  74. }
  75. pbsp_highest = pbsp;
  76. }
  77. pbsp++;
  78. }
  79. if (pbsp_highest) {
  80. printf("Error: board specific timing not found\n");
  81. printf("for data rate %lu MT/s\n", ddr_freq);
  82. printf("Trying to use the highest speed (%u) parameters\n",
  83. pbsp_highest->datarate_mhz_high);
  84. popts->clk_adjust = pbsp_highest->clk_adjust;
  85. popts->wrlvl_start = pbsp_highest->wrlvl_start;
  86. popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  87. popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  88. } else {
  89. panic("DIMM is not supported by this board");
  90. }
  91. found:
  92. debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
  93. pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
  94. debug("\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, ",
  95. pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2);
  96. debug("wrlvl_ctrl_3 0x%x\n", pbsp->wrlvl_ctl_3);
  97. /*
  98. * Factors to consider for half-strength driver enable:
  99. * - number of DIMMs installed
  100. */
  101. popts->half_strength_driver_enable = 0;
  102. /*
  103. * Write leveling override
  104. */
  105. popts->wrlvl_override = 1;
  106. popts->wrlvl_sample = 0xf;
  107. /*
  108. * rtt and rtt_wr override
  109. */
  110. popts->rtt_override = 0;
  111. /* Enable ZQ calibration */
  112. popts->zq_en = 1;
  113. /* DHC_EN =1, ODT = 75 Ohm */
  114. popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_OFF);
  115. popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_OFF);
  116. /* T1023 supports max DDR bus 32bit width, T1024 supports DDR 64bit,
  117. * force DDR bus width to 32bit for T1023
  118. */
  119. if (cpu->soc_ver == SVR_T1023)
  120. popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
  121. #ifdef CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32
  122. /* for DDR bus 32bit test on T1024 */
  123. popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
  124. #endif
  125. #ifdef CONFIG_TARGET_T1023RDB
  126. popts->wrlvl_ctl_2 = 0x07070606;
  127. popts->half_strength_driver_enable = 1;
  128. popts->cpo_sample = 0x43;
  129. #elif defined(CONFIG_TARGET_T1024RDB)
  130. /* optimize cpo for erratum A-009942 */
  131. popts->cpo_sample = 0x52;
  132. #endif
  133. }
  134. #ifdef CONFIG_SYS_DDR_RAW_TIMING
  135. /* 2GB discrete DDR4 MT40A512M8HX on T1023RDB */
  136. dimm_params_t ddr_raw_timing = {
  137. .n_ranks = 1,
  138. .rank_density = 0x80000000,
  139. .capacity = 0x80000000,
  140. .primary_sdram_width = 32,
  141. .ec_sdram_width = 8,
  142. .registered_dimm = 0,
  143. .mirrored_dimm = 0,
  144. .n_row_addr = 15,
  145. .n_col_addr = 10,
  146. .bank_addr_bits = 2,
  147. .bank_group_bits = 2,
  148. .edc_config = 0,
  149. .burst_lengths_bitmask = 0x0c,
  150. .tckmin_x_ps = 938,
  151. .tckmax_ps = 1500,
  152. .caslat_x = 0x000DFA00,
  153. .taa_ps = 13500,
  154. .trcd_ps = 13500,
  155. .trp_ps = 13500,
  156. .tras_ps = 33000,
  157. .trc_ps = 46500,
  158. .trfc1_ps = 260000,
  159. .trfc2_ps = 160000,
  160. .trfc4_ps = 110000,
  161. .tfaw_ps = 25000,
  162. .trrds_ps = 3700,
  163. .trrdl_ps = 5300,
  164. .tccdl_ps = 5355,
  165. .refresh_rate_ps = 7800000,
  166. .dq_mapping[0] = 0x0,
  167. .dq_mapping[1] = 0x0,
  168. .dq_mapping[2] = 0x0,
  169. .dq_mapping[3] = 0x0,
  170. .dq_mapping[4] = 0x0,
  171. .dq_mapping[5] = 0x0,
  172. .dq_mapping[6] = 0x0,
  173. .dq_mapping[7] = 0x0,
  174. .dq_mapping[8] = 0x0,
  175. .dq_mapping[9] = 0x0,
  176. .dq_mapping[10] = 0x0,
  177. .dq_mapping[11] = 0x0,
  178. .dq_mapping[12] = 0x0,
  179. .dq_mapping[13] = 0x0,
  180. .dq_mapping[14] = 0x0,
  181. .dq_mapping[15] = 0x0,
  182. .dq_mapping[16] = 0x0,
  183. .dq_mapping[17] = 0x0,
  184. .dq_mapping_ors = 1,
  185. };
  186. int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
  187. unsigned int controller_number,
  188. unsigned int dimm_number)
  189. {
  190. const char dimm_model[] = "Fixed DDR4 on board";
  191. if (((controller_number == 0) && (dimm_number == 0)) ||
  192. ((controller_number == 1) && (dimm_number == 0))) {
  193. memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
  194. memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
  195. memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
  196. }
  197. return 0;
  198. }
  199. #endif
  200. #if defined(CONFIG_DEEP_SLEEP)
  201. void board_mem_sleep_setup(void)
  202. {
  203. void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
  204. /* does not provide HW signals for power management */
  205. clrbits_8(cpld_base + 0x17, 0x40);
  206. /* Disable MCKE isolation */
  207. gpio_set_value(2, 0);
  208. udelay(1);
  209. }
  210. #endif
  211. int dram_init(void)
  212. {
  213. phys_size_t dram_size;
  214. #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
  215. #ifndef CONFIG_SYS_DDR_RAW_TIMING
  216. puts("Initializing....using SPD\n");
  217. #endif
  218. dram_size = fsl_ddr_sdram();
  219. #else
  220. /* DDR has been initialised by first stage boot loader */
  221. dram_size = fsl_ddr_sdram_size();
  222. #endif
  223. dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  224. dram_size *= 0x100000;
  225. #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
  226. fsl_dp_resume();
  227. #endif
  228. gd->ram_size = dram_size;
  229. return 0;
  230. }