cpld.c 2.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /**
  3. * Copyright 2014 Freescale Semiconductor
  4. *
  5. * Freescale T1024RDB board-specific CPLD controlling supports.
  6. *
  7. * The following macros need to be defined:
  8. */
  9. #include <common.h>
  10. #include <command.h>
  11. #include <asm/io.h>
  12. #include "cpld.h"
  13. u8 cpld_read(unsigned int reg)
  14. {
  15. void *p = (void *)CONFIG_SYS_CPLD_BASE;
  16. return in_8(p + reg);
  17. }
  18. void cpld_write(unsigned int reg, u8 value)
  19. {
  20. void *p = (void *)CONFIG_SYS_CPLD_BASE;
  21. out_8(p + reg, value);
  22. }
  23. /**
  24. * Set the boot bank to the alternate bank
  25. */
  26. void cpld_set_altbank(void)
  27. {
  28. u8 reg = CPLD_READ(flash_csr);
  29. reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK;
  30. CPLD_WRITE(flash_csr, reg);
  31. CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
  32. }
  33. /**
  34. * Set the boot bank to the default bank
  35. */
  36. void cpld_set_defbank(void)
  37. {
  38. u8 reg = CPLD_READ(flash_csr);
  39. reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK;
  40. CPLD_WRITE(flash_csr, reg);
  41. CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
  42. }
  43. static void cpld_dump_regs(void)
  44. {
  45. printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver));
  46. printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub));
  47. printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver));
  48. printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver));
  49. printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1));
  50. printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2));
  51. printf("int_status = 0x%02x\n", CPLD_READ(int_status));
  52. printf("flash_csr = 0x%02x\n", CPLD_READ(flash_csr));
  53. printf("fan_ctl_status = 0x%02x\n", CPLD_READ(fan_ctl_status));
  54. printf("led_ctl_status = 0x%02x\n", CPLD_READ(led_ctl_status));
  55. printf("sfp_ctl_status = 0x%02x\n", CPLD_READ(sfp_ctl_status));
  56. printf("misc_ctl_status = 0x%02x\n", CPLD_READ(misc_ctl_status));
  57. printf("boot_override = 0x%02x\n", CPLD_READ(boot_override));
  58. printf("boot_config1 = 0x%02x\n", CPLD_READ(boot_config1));
  59. printf("boot_config2 = 0x%02x\n", CPLD_READ(boot_config2));
  60. putc('\n');
  61. }
  62. int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  63. {
  64. int rc = 0;
  65. if (argc <= 1)
  66. return cmd_usage(cmdtp);
  67. if (strcmp(argv[1], "reset") == 0) {
  68. if (strcmp(argv[2], "altbank") == 0)
  69. cpld_set_altbank();
  70. else
  71. cpld_set_defbank();
  72. } else if (strcmp(argv[1], "dump") == 0) {
  73. cpld_dump_regs();
  74. } else {
  75. rc = cmd_usage(cmdtp);
  76. }
  77. return rc;
  78. }
  79. U_BOOT_CMD(
  80. cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
  81. "Reset the board or alternate bank",
  82. "reset - hard reset to default bank\n"
  83. "cpld reset altbank - reset to alternate bank\n"
  84. "cpld dump - display the CPLD registers\n"
  85. );