README 13 KB

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  1. T1024 SoC Overview
  2. ------------------
  3. The T1024/T1023 dual core and T1014/T1013 single core QorIQ communication processor
  4. combines two or one 64-bit Power Architecture e5500 core respectively with high
  5. performance datapath acceleration logic, and network peripheral bus interfaces
  6. required for networking and telecommunications. This processor can be used in
  7. applications such as enterprise WLAN access points, routers, switches, firewall
  8. and other packet processing intensive small enterprise and branch office appliances,
  9. and general-purpose embedded computing. Its high level of integration offers
  10. significant performance benefits and greatly helps to simplify board design.
  11. The T1024 SoC includes the following function and features:
  12. - two e5500 cores, each with a private 256 KB L2 cache
  13. - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)
  14. - Three levels of instructions: User, supervisor, and hypervisor
  15. - Independent boot and reset
  16. - Secure boot capability
  17. - 256 KB shared L3 CoreNet platform cache (CPC)
  18. - Interconnect CoreNet platform
  19. - CoreNet coherency manager supporting coherent and noncoherent transactions
  20. with prioritization and bandwidth allocation amongst CoreNet endpoints
  21. - 150 Gbps coherent read bandwidth
  22. - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
  23. - Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions:
  24. - Packet parsing, classification, and distribution
  25. - Queue management for scheduling, packet sequencing, and congestion management
  26. - Cryptography Acceleration (SEC 5.x)
  27. - IEEE 1588 support
  28. - Hardware buffer management for buffer allocation and deallocation
  29. - MACSEC on DPAA-based Ethernet ports
  30. - Ethernet interfaces
  31. - Four 1 Gbps Ethernet controllers
  32. - Parallel Ethernet interfaces
  33. - Two RGMII interfaces
  34. - High speed peripheral interfaces
  35. - Three PCI Express 2.0 controllers/ports running at up to 5 GHz
  36. - One SATA controller supporting 1.5 and 3.0 Gb/s operation
  37. - One QSGMII interface
  38. - Four SGMII interface supporting 1000 Mbps
  39. - Three SGMII interfaces supporting up to 2500 Mbps
  40. - 10GbE XFI or 10Base-KR interface
  41. - Additional peripheral interfaces
  42. - Two USB 2.0 controllers with integrated PHY
  43. - SD/eSDHC/eMMC
  44. - eSPI controller
  45. - Four I2C controllers
  46. - Four UARTs
  47. - Four GPIO controllers
  48. - Integrated flash controller (IFC)
  49. - LCD interface (DIU) with 12 bit dual data rate
  50. - Multicore programmable interrupt controller (PIC)
  51. - Two 8-channel DMA engines
  52. - Single source clocking implementation
  53. - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
  54. - QUICC Engine block
  55. - 32-bit RISC controller for flexible support of the communications peripherals
  56. - Serial DMA channel for receive and transmit on all serial channels
  57. - Two universal communication controllers, supporting TDM, HDLC, and UART
  58. T1023 Personality
  59. ------------------
  60. T1023 is a reduced personality of T1024 without QUICC Engine, DIU, and
  61. unavailable deep sleep. Rest of the blocks are almost same as T1024.
  62. Differences between T1024 and T1023
  63. Feature T1024 T1023
  64. QUICC Engine: yes no
  65. DIU: yes no
  66. Deep Sleep: yes no
  67. I2C controller: 4 3
  68. DDR: 64-bit 32-bit
  69. IFC: 32-bit 28-bit
  70. Package: 23x23 19x19
  71. T1024RDB board Overview
  72. -----------------------
  73. - Ethernet
  74. - Two on-board 10M/100M/1G bps RGMII ethernet ports
  75. - One on-board 10G bps Base-T port.
  76. - DDR Memory
  77. - Supports 64-bit 4GB DDR3L DIMM
  78. - PCIe
  79. - One on-board PCIe slot.
  80. - Two on-board PCIe Mini-PCIe connectors.
  81. - IFC/Local Bus
  82. - NOR: 128MB 16-bit NOR Flash
  83. - NAND: 1GB 8-bit NAND flash
  84. - CPLD: for system controlling with programable header on-board
  85. - USB
  86. - Supports two USB 2.0 ports with integrated PHYs
  87. - Two type A ports with 5V@1.5A per port.
  88. - SDHC
  89. - one SD connector supporting 1.8V/3.3V via J53.
  90. - SPI
  91. - On-board 64MB SPI flash
  92. - Other
  93. - Two Serial ports
  94. - Four I2C ports
  95. T1023RDB board Overview
  96. -----------------------
  97. - T1023 SoC integrating two 64-bit e5500 cores up to 1.4GHz
  98. - CoreNet fabric supporting coherent and noncoherent transactions with
  99. prioritization and bandwidth allocation
  100. - SDRAM memory: 2GB Micron MT40A512M8HX unbuffered 32-bit DDR4 w/o ECC
  101. - Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC
  102. - Ethernet interfaces:
  103. - one 1G RGMII port on-board(RTL8211FS PHY)
  104. - one 1G SGMII port on-board(RTL8211FS PHY)
  105. - one 2.5G SGMII port on-board(AQR105 PHY)
  106. - PCIe: Two Mini-PCIe connectors on-board.
  107. - SerDes: 4 lanes up to 10.3125GHz
  108. - NOR: 128MB S29GL01GS110TFIV10 Spansion NOR Flash
  109. - NAND: 512MB S34MS04G200BFI000 Spansion NAND Flash
  110. - eSPI: 64MB S25FL512SAGMFI010 Spansion SPI flash.
  111. - USB: one Type-A USB 2.0 port with internal PHY
  112. - eSDHC: support SD/MMC and eMMC card
  113. - 256Kbit M24256 I2C EEPROM
  114. - RTC: Real-time clock DS1339U on I2C bus
  115. - UART: one serial port on-board with RJ45 connector
  116. - Debugging: JTAG/COP for T1023 debugging
  117. Memory map on T1024RDB
  118. ----------------------
  119. Start Address End Address Description Size
  120. 0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
  121. 0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
  122. 0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
  123. 0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
  124. 0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
  125. 0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
  126. 0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
  127. 0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
  128. 0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
  129. 0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
  130. 0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB
  131. 0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB
  132. 0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB
  133. 0x0_0000_0000 0x0_ffff_ffff DDR 4GB
  134. 128MB NOR Flash Memory Layout
  135. -----------------------------
  136. Start Address End Address Definition Max size
  137. 0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB
  138. 0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB
  139. 0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
  140. 0xEFE00000 0xEFE3FFFF QE firmware (current bank) 256KB
  141. 0xED300000 0xEFDFFFFF rootfs (alt bank) 44MB
  142. 0xED000000 0xED2FFFFF Guest image #3 (alternate bank) 3MB
  143. 0xECD00000 0xECFFFFFF Guest image #2 (alternate bank) 3MB
  144. 0xECA00000 0xECCFFFFF Guest image #1 (alternate bank) 3MB
  145. 0xEC900000 0xEC9FFFFF HV config device tree(alt bank) 1MB
  146. 0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
  147. 0xEC700000 0xEC7FFFFF HV.uImage (alternate bank) 1MB
  148. 0xEC020000 0xEC6FFFFF Linux.uImage (alt bank) ~7MB
  149. 0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
  150. 0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB
  151. 0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB
  152. 0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
  153. 0xEBE00000 0xEBE3FFFF QE firmware (alt bank) 256KB
  154. 0xE9300000 0xEBDFFFFF rootfs (current bank) 44MB
  155. 0xE9000000 0xE92FFFFF Guest image #3 (current bank) 3MB
  156. 0xE8D00000 0xE8FFFFFF Guest image #2 (current bank) 3MB
  157. 0xE8A00000 0xE8CFFFFF Guest image #1 (current bank) 3MB
  158. 0xE8900000 0xE89FFFFF HV config device tree(cur bank) 1MB
  159. 0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB
  160. 0xE8700000 0xE87FFFFF HV.uImage (current bank) 1MB
  161. 0xE8020000 0xE86FFFFF Linux.uImage (current bank) ~7MB
  162. 0xE8000000 0xE801FFFF RCW (current bank) 128KB
  163. T1024/T1023 Clock frequency
  164. ---------------------------
  165. BIN Core DDR Platform FMan
  166. Bin1: 1400MHz 1600MT/s 400MHz 700MHz
  167. Bin2: 1200MHz 1600MT/s 400MHz 600MHz
  168. Bin3: 1000MHz 1600MT/s 400MHz 500MHz
  169. Software configurations and board settings
  170. ------------------------------------------
  171. 1. NOR boot:
  172. a. build NOR boot image
  173. $ make T1024RDB_defconfig
  174. $ make
  175. b. program u-boot.bin image to NOR flash
  176. => tftp 1000000 u-boot.bin
  177. => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
  178. on T1024RDB:
  179. set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
  180. on T1023RDB:
  181. set SW1[1:8] = '00010111', SW2[1] = '1', SW3[4] = '0' for NOR boot
  182. Switching between default bank0 and alternate bank4 on NOR flash
  183. To change boot source to vbank4:
  184. on T1024RDB:
  185. via software: run command 'cpld reset altbank' in U-Boot.
  186. via DIP-switch: set SW3[5:7] = '100'
  187. on T1023RDB:
  188. via software: run command 'switch bank4' in U-Boot.
  189. via DIP-switch: set SW3[5:7] = '100'
  190. To change boot source to vbank0:
  191. on T1024RDB:
  192. via software: run command 'cpld reset' in U-Boot.
  193. via DIP-Switch: set SW3[5:7] = '000'
  194. on T1023RDB:
  195. via software: run command 'switch bank0' in U-Boot.
  196. via DIP-switch: set SW3[5:7] = '000'
  197. 2. NAND Boot:
  198. a. build PBL image for NAND boot
  199. $ make T1024RDB_NAND_defconfig
  200. $ make
  201. b. program u-boot-with-spl-pbl.bin to NAND flash
  202. => tftp 1000000 u-boot-with-spl-pbl.bin
  203. => nand erase 0 $filesize
  204. => nand write 1000000 0 $filesize
  205. set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot
  206. 3. SPI Boot:
  207. a. build PBL image for SPI boot
  208. $ make T1024RDB_SPIFLASH_defconfig
  209. $ make
  210. b. program u-boot-with-spl-pbl.bin to SPI flash
  211. => tftp 1000000 u-boot-with-spl-pbl.bin
  212. => sf probe 0
  213. => sf erase 0 100000
  214. => sf write 1000000 0 $filesize
  215. => tftp 1000000 fsl_fman_ucode_t1024_xx.bin
  216. => sf erase 100000 100000
  217. => sf write 1000000 110000 20000
  218. set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
  219. 4. SD Boot:
  220. a. build PBL image for SD boot
  221. $ make T1024RDB_SDCARD_defconfig
  222. $ make
  223. b. program u-boot-with-spl-pbl.bin to SD/MMC card
  224. => tftp 1000000 u-boot-with-spl-pbl.bin
  225. => mmc write 1000000 8 0x7f0
  226. => tftp 1000000 fsl_fman_ucode_t1024_xx.bin
  227. => mmc write 1000000 0x820 80
  228. set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
  229. SW3[3] = '1' for SD card(or 'switch sd' by software)
  230. SW3[3] = '0' for eMMC (or 'switch emmc' by software)
  231. device tree support and how to enable it for different configs
  232. --------------------------------------------------------------
  233. device tree support is available for t1024rdb for below mentioned boot,
  234. 1. nor boot
  235. 2. nand boot
  236. 3. sd boot
  237. 4. spiflash boot
  238. to enable device tree support for other boot, below configs need to be
  239. enabled in relative defconfig file,
  240. 1. config_default_device_tree="t1024rdb" (change default device tree name if required)
  241. 2. config_of_control
  242. 3. config_mpc85xx_have_reset_vector if reset vector is located at
  243. config_reset_vector_address - 0xffc
  244. if device tree support is enabled in defconfig,
  245. 1. use 'u-boot-with-dtb.bin' for nor boot.
  246. 2. use 'u-boot-with-spl-pbl.bin' for other boot.
  247. 2-stage NAND/SPI/SD boot loader
  248. -------------------------------
  249. PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
  250. SPL further initializes DDR using SPD and environment variables
  251. and copy U-Boot(768 KB) from NAND/SPI/SD device to DDR.
  252. Finally SPL transers control to U-Boot for futher booting.
  253. SPL has following features:
  254. - Executes within 256K
  255. - No relocation required
  256. Run time view of SPL framework
  257. -------------------------------------------------
  258. |Area | Address |
  259. -------------------------------------------------
  260. |SecureBoot header | 0xFFFC0000 (32KB) |
  261. -------------------------------------------------
  262. |GD, BD | 0xFFFC8000 (4KB) |
  263. -------------------------------------------------
  264. |ENV | 0xFFFC9000 (8KB) |
  265. -------------------------------------------------
  266. |HEAP | 0xFFFCB000 (30KB) |
  267. -------------------------------------------------
  268. |STACK | 0xFFFD8000 (22KB) |
  269. -------------------------------------------------
  270. |U-Boot SPL | 0xFFFD8000 (160KB) |
  271. -------------------------------------------------
  272. NAND Flash memory Map on T1024RDB
  273. -------------------------------------------------------------
  274. Start End Definition Size
  275. 0x000000 0x0FFFFF U-Boot 1MB(2 block)
  276. 0x100000 0x17FFFF U-Boot env 512KB(1 block)
  277. 0x180000 0x1FFFFF FMAN Ucode 512KB(1 block)
  278. 0x200000 0x27FFFF QE Firmware 512KB(1 block)
  279. NAND Flash memory Map on T1023RDB
  280. ----------------------------------------------------
  281. Start End Definition Size
  282. 0x000000 0x0FFFFF U-Boot 1MB
  283. 0x100000 0x15FFFF U-Boot env 8KB
  284. 0x160000 0x17FFFF FMAN Ucode 128KB
  285. SD Card memory Map on T102xRDB
  286. ----------------------------------------------------
  287. Block #blocks Definition Size
  288. 0x008 2048 U-Boot img 1MB
  289. 0x800 0016 U-Boot env 8KB
  290. 0x820 0256 FMAN Ucode 128KB
  291. 0x920 0256 QE Firmware 128KB(only T1024RDB)
  292. 64MB SPI Flash memory Map on T102xRDB
  293. ----------------------------------------------------
  294. Start End Definition Size
  295. 0x000000 0x0FFFFF U-Boot img 1MB
  296. 0x100000 0x101FFF U-Boot env 8KB
  297. 0x110000 0x12FFFF FMAN Ucode 128KB
  298. 0x130000 0x14FFFF QE Firmware 128KB(only T1024RDB)
  299. 0x300000 0x3FFFFF device tree 128KB
  300. 0x400000 0x9FFFFF Linux kernel 6MB
  301. 0xa00000 0x3FFFFFF rootfs 54MB
  302. For more details, please refer to T1024RDB/T1023RDB User Guide
  303. and Freescale QorIQ SDK Infocenter document.