mx6ullevk.c 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Freescale Semiconductor, Inc.
  4. */
  5. #include <init.h>
  6. #include <asm/arch/clock.h>
  7. #include <asm/arch/iomux.h>
  8. #include <asm/arch/imx-regs.h>
  9. #include <asm/arch/crm_regs.h>
  10. #include <asm/arch/mx6-pins.h>
  11. #include <asm/arch/sys_proto.h>
  12. #include <asm/global_data.h>
  13. #include <asm/gpio.h>
  14. #include <asm/mach-imx/iomux-v3.h>
  15. #include <asm/mach-imx/boot_mode.h>
  16. #include <asm/io.h>
  17. #include <common.h>
  18. #include <env.h>
  19. #include <fsl_esdhc_imx.h>
  20. #include <linux/sizes.h>
  21. #include <mmc.h>
  22. #include <miiphy.h>
  23. DECLARE_GLOBAL_DATA_PTR;
  24. #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  25. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  26. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  27. int dram_init(void)
  28. {
  29. gd->ram_size = imx_ddr_size();
  30. return 0;
  31. }
  32. static iomux_v3_cfg_t const uart1_pads[] = {
  33. MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  34. MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  35. };
  36. static void setup_iomux_uart(void)
  37. {
  38. imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  39. }
  40. int board_mmc_get_env_dev(int devno)
  41. {
  42. return devno;
  43. }
  44. int mmc_map_to_kernel_blk(int devno)
  45. {
  46. return devno;
  47. }
  48. int board_early_init_f(void)
  49. {
  50. setup_iomux_uart();
  51. return 0;
  52. }
  53. #ifdef CONFIG_FEC_MXC
  54. static int setup_fec(int fec_id)
  55. {
  56. struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  57. int ret;
  58. if (fec_id == 0) {
  59. /*
  60. * Use 50MHz anatop loopback REF_CLK1 for ENET1,
  61. * clear gpr1[13], set gpr1[17].
  62. */
  63. clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
  64. IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
  65. } else {
  66. /*
  67. * Use 50MHz anatop loopback REF_CLK2 for ENET2,
  68. * clear gpr1[14], set gpr1[18].
  69. */
  70. clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
  71. IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
  72. }
  73. ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
  74. if (ret)
  75. return ret;
  76. enable_enet_clk(1);
  77. return 0;
  78. }
  79. int board_phy_config(struct phy_device *phydev)
  80. {
  81. phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
  82. if (phydev->drv->config)
  83. phydev->drv->config(phydev);
  84. return 0;
  85. }
  86. #endif
  87. int board_init(void)
  88. {
  89. /* Address of boot parameters */
  90. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  91. #ifdef CONFIG_FEC_MXC
  92. setup_fec(CONFIG_FEC_ENET_DEV);
  93. #endif
  94. return 0;
  95. }
  96. #ifdef CONFIG_CMD_BMODE
  97. static const struct boot_mode board_boot_modes[] = {
  98. /* 4 bit bus width */
  99. {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
  100. {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  101. {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
  102. {NULL, 0},
  103. };
  104. #endif
  105. int board_late_init(void)
  106. {
  107. #ifdef CONFIG_CMD_BMODE
  108. add_board_boot_modes(board_boot_modes);
  109. #endif
  110. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  111. if (is_cpu_type(MXC_CPU_MX6ULZ))
  112. env_set("board_name", "ULZ-EVK");
  113. else
  114. env_set("board_name", "EVK");
  115. env_set("board_rev", "14X14");
  116. #endif
  117. return 0;
  118. }
  119. int checkboard(void)
  120. {
  121. if (is_cpu_type(MXC_CPU_MX6ULZ))
  122. puts("Board: MX6ULZ 14x14 EVK\n");
  123. else
  124. puts("Board: MX6ULL 14x14 EVK\n");
  125. return 0;
  126. }