imximage.cfg 2.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2014 Freescale Semiconductor, Inc.
  4. */
  5. #define __ASSEMBLY__
  6. #include <config.h>
  7. /* image version */
  8. IMAGE_VERSION 2
  9. /*
  10. * Boot Device : one of
  11. * spi/sd/nand/onenand, qspi/nor
  12. */
  13. BOOT_FROM sd
  14. /*
  15. * Device Configuration Data (DCD)
  16. *
  17. * Each entry must have the format:
  18. * Addr-type Address Value
  19. *
  20. * where:
  21. * Addr-type register length (1,2 or 4 bytes)
  22. * Address absolute address of the register
  23. * value value to be stored in the register
  24. */
  25. /* Enable all clocks */
  26. DATA 4 0x020c4068 0xffffffff
  27. DATA 4 0x020c406c 0xffffffff
  28. DATA 4 0x020c4070 0xffffffff
  29. DATA 4 0x020c4074 0xffffffff
  30. DATA 4 0x020c4078 0xffffffff
  31. DATA 4 0x020c407c 0xffffffff
  32. DATA 4 0x020c4080 0xffffffff
  33. DATA 4 0x020c4084 0xffffffff
  34. /* IOMUX - DDR IO Type */
  35. DATA 4 0x020e0618 0x000c0000
  36. DATA 4 0x020e05fc 0x00000000
  37. /* Clock */
  38. DATA 4 0x020e032c 0x00000030
  39. /* Address */
  40. DATA 4 0x020e0300 0x00000030
  41. DATA 4 0x020e02fc 0x00000030
  42. DATA 4 0x020e05f4 0x00000030
  43. /* Control */
  44. DATA 4 0x020e0340 0x00000030
  45. DATA 4 0x020e0320 0x00000000
  46. DATA 4 0x020e0310 0x00000030
  47. DATA 4 0x020e0314 0x00000030
  48. DATA 4 0x020e0614 0x00000030
  49. /* Data Strobe */
  50. DATA 4 0x020e05f8 0x00020000
  51. DATA 4 0x020e0330 0x00000030
  52. DATA 4 0x020e0334 0x00000030
  53. DATA 4 0x020e0338 0x00000030
  54. DATA 4 0x020e033c 0x00000030
  55. /* Data */
  56. DATA 4 0x020e0608 0x00020000
  57. DATA 4 0x020e060c 0x00000030
  58. DATA 4 0x020e0610 0x00000030
  59. DATA 4 0x020e061c 0x00000030
  60. DATA 4 0x020e0620 0x00000030
  61. DATA 4 0x020e02ec 0x00000030
  62. DATA 4 0x020e02f0 0x00000030
  63. DATA 4 0x020e02f4 0x00000030
  64. DATA 4 0x020e02f8 0x00000030
  65. /* Calibrations - ZQ */
  66. DATA 4 0x021b0800 0xa1390003
  67. /* Write leveling */
  68. DATA 4 0x021b080c 0x002C003D
  69. DATA 4 0x021b0810 0x00110046
  70. /* DQS Read Gate */
  71. DATA 4 0x021b083c 0x4160016C
  72. DATA 4 0x021b0840 0x013C016C
  73. /* Read/Write Delay */
  74. DATA 4 0x021b0848 0x46424446
  75. DATA 4 0x021b0850 0x3A3C3C3A
  76. DATA 4 0x021b08c0 0x2492244A
  77. /* read data bit delay */
  78. DATA 4 0x021b081c 0x33333333
  79. DATA 4 0x021b0820 0x33333333
  80. DATA 4 0x021b0824 0x33333333
  81. DATA 4 0x021b0828 0x33333333
  82. /* Complete calibration by forced measurement */
  83. DATA 4 0x021b08b8 0x00000800
  84. /* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */
  85. DATA 4 0x021b0004 0x0002002d
  86. DATA 4 0x021b0008 0x00333030
  87. DATA 4 0x021b000c 0x676b52f3
  88. DATA 4 0x021b0010 0xb66d8b63
  89. DATA 4 0x021b0014 0x01ff00db
  90. DATA 4 0x021b0018 0x00011740
  91. DATA 4 0x021b001c 0x00008000
  92. DATA 4 0x021b002c 0x000026d2
  93. DATA 4 0x021b0030 0x006b1023
  94. DATA 4 0x021b0040 0x0000007f
  95. DATA 4 0x021b0000 0x85190000
  96. /* Initialize MT41K256M16HA-125 - MR2 */
  97. DATA 4 0x021b001c 0x04008032
  98. /* MR3 */
  99. DATA 4 0x021b001c 0x00008033
  100. /* MR1 */
  101. DATA 4 0x021b001c 0x00068031
  102. /* MR0 */
  103. DATA 4 0x021b001c 0x05208030
  104. /* DDR device ZQ calibration */
  105. DATA 4 0x021b001c 0x04008040
  106. /* Final DDR setup, before operation start */
  107. DATA 4 0x021b0020 0x00000800
  108. DATA 4 0x021b0818 0x00022227
  109. DATA 4 0x021b0004 0x0002556d
  110. DATA 4 0x021b0404 0x00011006
  111. DATA 4 0x021b001c 0x00000000