mx6sllevk.c 2.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Freescale Semiconductor, Inc.
  4. */
  5. #include <init.h>
  6. #include <asm/arch/clock.h>
  7. #include <asm/arch/crm_regs.h>
  8. #include <asm/arch/iomux.h>
  9. #include <asm/arch/imx-regs.h>
  10. #include <asm/arch/mx6-pins.h>
  11. #include <asm/arch/sys_proto.h>
  12. #include <asm/global_data.h>
  13. #include <asm/gpio.h>
  14. #include <asm/mach-imx/iomux-v3.h>
  15. #include <asm/mach-imx/boot_mode.h>
  16. #include <asm/io.h>
  17. #include <common.h>
  18. #include <linux/sizes.h>
  19. #include <mmc.h>
  20. #include <power/pmic.h>
  21. #include <power/pfuze100_pmic.h>
  22. #include "../common/pfuze.h"
  23. DECLARE_GLOBAL_DATA_PTR;
  24. #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  25. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  26. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  27. int dram_init(void)
  28. {
  29. gd->ram_size = imx_ddr_size();
  30. return 0;
  31. }
  32. static iomux_v3_cfg_t const uart1_pads[] = {
  33. MX6_PAD_UART1_TXD__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  34. MX6_PAD_UART1_RXD__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  35. };
  36. static iomux_v3_cfg_t const wdog_pads[] = {
  37. MX6_PAD_WDOG_B__WDOG1_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  38. };
  39. static void setup_iomux_uart(void)
  40. {
  41. imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  42. }
  43. #ifdef CONFIG_DM_PMIC_PFUZE100
  44. int power_init_board(void)
  45. {
  46. struct udevice *dev;
  47. int ret;
  48. u32 dev_id, rev_id, i;
  49. u32 switch_num = 6;
  50. u32 offset = PFUZE100_SW1CMODE;
  51. ret = pmic_get("pfuze100@08", &dev);
  52. if (ret == -ENODEV)
  53. return 0;
  54. if (ret != 0)
  55. return ret;
  56. dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
  57. rev_id = pmic_reg_read(dev, PFUZE100_REVID);
  58. printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
  59. /* Init mode to APS_PFM */
  60. pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);
  61. for (i = 0; i < switch_num - 1; i++)
  62. pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM);
  63. /* set SW1AB staby volatage 0.975V */
  64. pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b);
  65. /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
  66. pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40);
  67. /* set SW1C staby volatage 0.975V */
  68. pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x1b);
  69. /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
  70. pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40);
  71. return 0;
  72. }
  73. #endif
  74. int board_early_init_f(void)
  75. {
  76. setup_iomux_uart();
  77. return 0;
  78. }
  79. int board_init(void)
  80. {
  81. /* Address of boot parameters */
  82. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  83. return 0;
  84. }
  85. int board_late_init(void)
  86. {
  87. imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  88. return 0;
  89. }
  90. int checkboard(void)
  91. {
  92. puts("Board: MX6SLL EVK\n");
  93. return 0;
  94. }
  95. int board_mmc_get_env_dev(int devno)
  96. {
  97. return devno;
  98. }
  99. int mmc_map_to_kernel_blk(int devno)
  100. {
  101. return devno;
  102. }