mx6sabreauto.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Freescale Semiconductor, Inc.
  4. *
  5. * Author: Fabio Estevam <fabio.estevam@freescale.com>
  6. */
  7. #include <common.h>
  8. #include <image.h>
  9. #include <init.h>
  10. #include <net.h>
  11. #include <asm/global_data.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/clock.h>
  14. #include <asm/arch/imx-regs.h>
  15. #include <asm/arch/iomux.h>
  16. #include <asm/arch/mx6-pins.h>
  17. #include <env.h>
  18. #include <linux/errno.h>
  19. #include <asm/gpio.h>
  20. #include <asm/mach-imx/iomux-v3.h>
  21. #include <asm/mach-imx/mxc_i2c.h>
  22. #include <asm/mach-imx/boot_mode.h>
  23. #include <asm/mach-imx/spi.h>
  24. #include <mmc.h>
  25. #include <fsl_esdhc_imx.h>
  26. #include <miiphy.h>
  27. #include <asm/arch/sys_proto.h>
  28. #include <i2c.h>
  29. #include <input.h>
  30. #include <asm/arch/mxc_hdmi.h>
  31. #include <asm/mach-imx/video.h>
  32. #include <asm/arch/crm_regs.h>
  33. #include <pca953x.h>
  34. #include <power/pmic.h>
  35. #include <power/pfuze100_pmic.h>
  36. #include "../common/pfuze.h"
  37. DECLARE_GLOBAL_DATA_PTR;
  38. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  39. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  40. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  41. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  42. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  43. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  44. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  45. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  46. #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  47. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  48. PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  49. #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
  50. #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
  51. PAD_CTL_SRE_FAST)
  52. #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
  53. #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  54. #define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  55. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  56. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  57. #define I2C_PMIC 1
  58. int dram_init(void)
  59. {
  60. gd->ram_size = imx_ddr_size();
  61. return 0;
  62. }
  63. static iomux_v3_cfg_t const uart4_pads[] = {
  64. IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  65. IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  66. };
  67. /* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
  68. static struct i2c_pads_info mx6q_i2c_pad_info1 = {
  69. .scl = {
  70. .i2c_mode = MX6Q_PAD_EIM_EB2__I2C2_SCL | PC,
  71. .gpio_mode = MX6Q_PAD_EIM_EB2__GPIO2_IO30 | PC,
  72. .gp = IMX_GPIO_NR(2, 30)
  73. },
  74. .sda = {
  75. .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
  76. .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
  77. .gp = IMX_GPIO_NR(4, 13)
  78. }
  79. };
  80. static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
  81. .scl = {
  82. .i2c_mode = MX6DL_PAD_EIM_EB2__I2C2_SCL | PC,
  83. .gpio_mode = MX6DL_PAD_EIM_EB2__GPIO2_IO30 | PC,
  84. .gp = IMX_GPIO_NR(2, 30)
  85. },
  86. .sda = {
  87. .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
  88. .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
  89. .gp = IMX_GPIO_NR(4, 13)
  90. }
  91. };
  92. #ifndef CONFIG_SYS_FLASH_CFI
  93. /*
  94. * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
  95. * Compass Sensor, Accelerometer, Res Touch
  96. */
  97. static struct i2c_pads_info mx6q_i2c_pad_info2 = {
  98. .scl = {
  99. .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
  100. .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
  101. .gp = IMX_GPIO_NR(1, 3)
  102. },
  103. .sda = {
  104. .i2c_mode = MX6Q_PAD_EIM_D18__I2C3_SDA | PC,
  105. .gpio_mode = MX6Q_PAD_EIM_D18__GPIO3_IO18 | PC,
  106. .gp = IMX_GPIO_NR(3, 18)
  107. }
  108. };
  109. static struct i2c_pads_info mx6dl_i2c_pad_info2 = {
  110. .scl = {
  111. .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
  112. .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
  113. .gp = IMX_GPIO_NR(1, 3)
  114. },
  115. .sda = {
  116. .i2c_mode = MX6DL_PAD_EIM_D18__I2C3_SDA | PC,
  117. .gpio_mode = MX6DL_PAD_EIM_D18__GPIO3_IO18 | PC,
  118. .gp = IMX_GPIO_NR(3, 18)
  119. }
  120. };
  121. #endif
  122. static iomux_v3_cfg_t const i2c3_pads[] = {
  123. IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  124. };
  125. static iomux_v3_cfg_t const port_exp[] = {
  126. IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  127. };
  128. #ifdef CONFIG_MTD_NOR_FLASH
  129. static iomux_v3_cfg_t const eimnor_pads[] = {
  130. IOMUX_PADS(PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  131. IOMUX_PADS(PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  132. IOMUX_PADS(PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  133. IOMUX_PADS(PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  134. IOMUX_PADS(PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  135. IOMUX_PADS(PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  136. IOMUX_PADS(PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  137. IOMUX_PADS(PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  138. IOMUX_PADS(PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  139. IOMUX_PADS(PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  140. IOMUX_PADS(PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  141. IOMUX_PADS(PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  142. IOMUX_PADS(PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  143. IOMUX_PADS(PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  144. IOMUX_PADS(PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  145. IOMUX_PADS(PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  146. IOMUX_PADS(PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  147. IOMUX_PADS(PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  148. IOMUX_PADS(PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  149. IOMUX_PADS(PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  150. IOMUX_PADS(PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  151. IOMUX_PADS(PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  152. IOMUX_PADS(PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  153. IOMUX_PADS(PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  154. IOMUX_PADS(PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  155. IOMUX_PADS(PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  156. IOMUX_PADS(PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  157. IOMUX_PADS(PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  158. IOMUX_PADS(PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  159. IOMUX_PADS(PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  160. IOMUX_PADS(PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  161. IOMUX_PADS(PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  162. IOMUX_PADS(PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  163. IOMUX_PADS(PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  164. IOMUX_PADS(PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  165. IOMUX_PADS(PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  166. IOMUX_PADS(PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  167. IOMUX_PADS(PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  168. IOMUX_PADS(PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  169. IOMUX_PADS(PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  170. IOMUX_PADS(PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  171. IOMUX_PADS(PAD_EIM_RW__EIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL)),
  172. IOMUX_PADS(PAD_EIM_CS0__EIM_CS0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  173. };
  174. static void eimnor_cs_setup(void)
  175. {
  176. struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
  177. writel(0x00020181, &weim_regs->cs0gcr1);
  178. writel(0x00000001, &weim_regs->cs0gcr2);
  179. writel(0x0a020000, &weim_regs->cs0rcr1);
  180. writel(0x0000c000, &weim_regs->cs0rcr2);
  181. writel(0x0804a240, &weim_regs->cs0wcr1);
  182. writel(0x00000120, &weim_regs->wcr);
  183. set_chipselect_size(CS0_128);
  184. }
  185. static void eim_clk_setup(void)
  186. {
  187. struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  188. int cscmr1, ccgr6;
  189. /* Turn off EIM clock */
  190. ccgr6 = readl(&imx_ccm->CCGR6);
  191. ccgr6 &= ~(0x3 << 10);
  192. writel(ccgr6, &imx_ccm->CCGR6);
  193. /*
  194. * Configure clk_eim_slow_sel = 00 --> derive clock from AXI clk root
  195. * and aclk_eim_slow_podf = 01 --> divide by 2
  196. * so that we can have EIM at the maximum clock of 132MHz
  197. */
  198. cscmr1 = readl(&imx_ccm->cscmr1);
  199. cscmr1 &= ~(MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK |
  200. MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK);
  201. cscmr1 |= (1 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET);
  202. writel(cscmr1, &imx_ccm->cscmr1);
  203. /* Turn on EIM clock */
  204. ccgr6 |= (0x3 << 10);
  205. writel(ccgr6, &imx_ccm->CCGR6);
  206. }
  207. static void setup_iomux_eimnor(void)
  208. {
  209. SETUP_IOMUX_PADS(eimnor_pads);
  210. gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
  211. eimnor_cs_setup();
  212. }
  213. #endif
  214. static iomux_v3_cfg_t const usdhc3_pads[] = {
  215. IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  216. IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  217. IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  218. IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  219. IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  220. IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  221. IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  222. IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  223. IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  224. IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  225. IOMUX_PADS(PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  226. IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  227. };
  228. static void setup_iomux_uart(void)
  229. {
  230. SETUP_IOMUX_PADS(uart4_pads);
  231. }
  232. #ifdef CONFIG_FSL_ESDHC_IMX
  233. static struct fsl_esdhc_cfg usdhc_cfg[1] = {
  234. {USDHC3_BASE_ADDR},
  235. };
  236. int board_mmc_getcd(struct mmc *mmc)
  237. {
  238. gpio_direction_input(IMX_GPIO_NR(6, 15));
  239. return !gpio_get_value(IMX_GPIO_NR(6, 15));
  240. }
  241. int board_mmc_init(struct bd_info *bis)
  242. {
  243. SETUP_IOMUX_PADS(usdhc3_pads);
  244. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  245. return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  246. }
  247. #endif
  248. #ifdef CONFIG_NAND_MXS
  249. static iomux_v3_cfg_t gpmi_pads[] = {
  250. IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  251. IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  252. IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  253. IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0)),
  254. IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  255. IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  256. IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  257. IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  258. IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  259. IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  260. IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  261. IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  262. IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  263. IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  264. IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  265. IOMUX_PADS(PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL1)),
  266. };
  267. static void setup_gpmi_nand(void)
  268. {
  269. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  270. /* config gpmi nand iomux */
  271. SETUP_IOMUX_PADS(gpmi_pads);
  272. setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
  273. MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
  274. MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)));
  275. /* enable apbh clock gating */
  276. setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  277. }
  278. #endif
  279. u32 get_board_rev(void)
  280. {
  281. int rev = nxp_board_rev();
  282. return (get_cpu_rev() & ~(0xF << 8)) | rev;
  283. }
  284. static int ar8031_phy_fixup(struct phy_device *phydev)
  285. {
  286. unsigned short val;
  287. /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
  288. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
  289. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
  290. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
  291. val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
  292. val &= 0xffe3;
  293. val |= 0x18;
  294. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
  295. /* introduce tx clock delay */
  296. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
  297. val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
  298. val |= 0x0100;
  299. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
  300. return 0;
  301. }
  302. int board_phy_config(struct phy_device *phydev)
  303. {
  304. ar8031_phy_fixup(phydev);
  305. if (phydev->drv->config)
  306. phydev->drv->config(phydev);
  307. return 0;
  308. }
  309. #if defined(CONFIG_VIDEO_IPUV3)
  310. static void disable_lvds(struct display_info_t const *dev)
  311. {
  312. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  313. clrbits_le32(&iomux->gpr[2],
  314. IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
  315. IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
  316. }
  317. static void do_enable_hdmi(struct display_info_t const *dev)
  318. {
  319. disable_lvds(dev);
  320. imx_enable_hdmi_phy();
  321. }
  322. struct display_info_t const displays[] = {{
  323. .bus = -1,
  324. .addr = 0,
  325. .pixfmt = IPU_PIX_FMT_RGB666,
  326. .detect = NULL,
  327. .enable = NULL,
  328. .mode = {
  329. .name = "Hannstar-XGA",
  330. .refresh = 60,
  331. .xres = 1024,
  332. .yres = 768,
  333. .pixclock = 15385,
  334. .left_margin = 220,
  335. .right_margin = 40,
  336. .upper_margin = 21,
  337. .lower_margin = 7,
  338. .hsync_len = 60,
  339. .vsync_len = 10,
  340. .sync = FB_SYNC_EXT,
  341. .vmode = FB_VMODE_NONINTERLACED
  342. } }, {
  343. .bus = -1,
  344. .addr = 0,
  345. .pixfmt = IPU_PIX_FMT_RGB24,
  346. .detect = detect_hdmi,
  347. .enable = do_enable_hdmi,
  348. .mode = {
  349. .name = "HDMI",
  350. .refresh = 60,
  351. .xres = 1024,
  352. .yres = 768,
  353. .pixclock = 15385,
  354. .left_margin = 220,
  355. .right_margin = 40,
  356. .upper_margin = 21,
  357. .lower_margin = 7,
  358. .hsync_len = 60,
  359. .vsync_len = 10,
  360. .sync = FB_SYNC_EXT,
  361. .vmode = FB_VMODE_NONINTERLACED,
  362. } } };
  363. size_t display_count = ARRAY_SIZE(displays);
  364. iomux_v3_cfg_t const backlight_pads[] = {
  365. IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  366. };
  367. static void setup_iomux_backlight(void)
  368. {
  369. gpio_request(IMX_GPIO_NR(2, 9), "backlight");
  370. gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
  371. SETUP_IOMUX_PADS(backlight_pads);
  372. }
  373. static void setup_display(void)
  374. {
  375. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  376. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  377. int reg;
  378. setup_iomux_backlight();
  379. enable_ipu_clock();
  380. imx_setup_hdmi();
  381. /* Turn on LDB_DI0 and LDB_DI1 clocks */
  382. reg = readl(&mxc_ccm->CCGR3);
  383. reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
  384. writel(reg, &mxc_ccm->CCGR3);
  385. /* Set LDB_DI0 and LDB_DI1 clk select to 3b'011 */
  386. reg = readl(&mxc_ccm->cs2cdr);
  387. reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
  388. MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
  389. reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
  390. (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
  391. writel(reg, &mxc_ccm->cs2cdr);
  392. reg = readl(&mxc_ccm->cscmr2);
  393. reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
  394. writel(reg, &mxc_ccm->cscmr2);
  395. reg = readl(&mxc_ccm->chsccdr);
  396. reg |= (CHSCCDR_CLK_SEL_LDB_DI0
  397. << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  398. reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
  399. MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
  400. writel(reg, &mxc_ccm->chsccdr);
  401. reg = IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
  402. IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
  403. IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
  404. IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
  405. IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
  406. IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
  407. IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
  408. IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED;
  409. writel(reg, &iomux->gpr[2]);
  410. reg = readl(&iomux->gpr[3]);
  411. reg &= ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
  412. IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
  413. reg |= (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
  414. IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) |
  415. (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
  416. IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET);
  417. writel(reg, &iomux->gpr[3]);
  418. }
  419. #endif /* CONFIG_VIDEO_IPUV3 */
  420. /*
  421. * Do not overwrite the console
  422. * Use always serial for U-Boot console
  423. */
  424. int overwrite_console(void)
  425. {
  426. return 1;
  427. }
  428. int board_early_init_f(void)
  429. {
  430. setup_iomux_uart();
  431. #ifdef CONFIG_NAND_MXS
  432. setup_gpmi_nand();
  433. #endif
  434. #ifdef CONFIG_MTD_NOR_FLASH
  435. eim_clk_setup();
  436. #endif
  437. return 0;
  438. }
  439. int board_init(void)
  440. {
  441. /* address of boot parameters */
  442. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  443. /* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
  444. if (is_mx6dq() || is_mx6dqp())
  445. setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
  446. else
  447. setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
  448. /* I2C 3 Steer */
  449. gpio_request(IMX_GPIO_NR(5, 4), "steer logic");
  450. gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
  451. SETUP_IOMUX_PADS(i2c3_pads);
  452. #ifndef CONFIG_SYS_FLASH_CFI
  453. if (is_mx6dq() || is_mx6dqp())
  454. setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2);
  455. else
  456. setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2);
  457. #endif
  458. gpio_request(IMX_GPIO_NR(1, 15), "expander en");
  459. gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
  460. SETUP_IOMUX_PADS(port_exp);
  461. #ifdef CONFIG_VIDEO_IPUV3
  462. setup_display();
  463. #endif
  464. #ifdef CONFIG_MTD_NOR_FLASH
  465. setup_iomux_eimnor();
  466. #endif
  467. return 0;
  468. }
  469. #ifdef CONFIG_MXC_SPI
  470. int board_spi_cs_gpio(unsigned bus, unsigned cs)
  471. {
  472. return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
  473. }
  474. #endif
  475. int power_init_board(void)
  476. {
  477. struct pmic *p;
  478. unsigned int value;
  479. p = pfuze_common_init(I2C_PMIC);
  480. if (!p)
  481. return -ENODEV;
  482. if (is_mx6dqp()) {
  483. /* set SW2 staby volatage 0.975V*/
  484. pmic_reg_read(p, PFUZE100_SW2STBY, &value);
  485. value &= ~0x3f;
  486. value |= 0x17;
  487. pmic_reg_write(p, PFUZE100_SW2STBY, value);
  488. }
  489. return pfuze_mode_init(p, APS_PFM);
  490. }
  491. #ifdef CONFIG_CMD_BMODE
  492. static const struct boot_mode board_boot_modes[] = {
  493. /* 4 bit bus width */
  494. {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  495. {NULL, 0},
  496. };
  497. #endif
  498. int board_late_init(void)
  499. {
  500. #ifdef CONFIG_CMD_BMODE
  501. add_board_boot_modes(board_boot_modes);
  502. #endif
  503. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  504. env_set("board_name", "SABREAUTO");
  505. if (is_mx6dqp())
  506. env_set("board_rev", "MX6QP");
  507. else if (is_mx6dq())
  508. env_set("board_rev", "MX6Q");
  509. else if (is_mx6sdl())
  510. env_set("board_rev", "MX6DL");
  511. #endif
  512. return 0;
  513. }
  514. int checkboard(void)
  515. {
  516. printf("Board: MX6Q-Sabreauto rev%c\n", nxp_board_rev_string());
  517. return 0;
  518. }
  519. #ifdef CONFIG_USB_EHCI_MX6
  520. int board_ehci_hcd_init(int port)
  521. {
  522. switch (port) {
  523. case 0:
  524. /*
  525. * Set daisy chain for otg_pin_id on 6q.
  526. * For 6dl, this bit is reserved.
  527. */
  528. imx_iomux_set_gpr_register(1, 13, 1, 0);
  529. break;
  530. case 1:
  531. break;
  532. default:
  533. printf("MXC USB port %d not yet supported\n", port);
  534. return -EINVAL;
  535. }
  536. return 0;
  537. }
  538. #endif
  539. #ifdef CONFIG_SPL_BUILD
  540. #include <asm/arch/mx6-ddr.h>
  541. #include <spl.h>
  542. #include <linux/libfdt.h>
  543. #ifdef CONFIG_SPL_OS_BOOT
  544. int spl_start_uboot(void)
  545. {
  546. return 0;
  547. }
  548. #endif
  549. static void ccgr_init(void)
  550. {
  551. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  552. writel(0x00C03F3F, &ccm->CCGR0);
  553. writel(0x0030FC03, &ccm->CCGR1);
  554. writel(0x0FFFC000, &ccm->CCGR2);
  555. writel(0x3FF00000, &ccm->CCGR3);
  556. writel(0x00FFF300, &ccm->CCGR4);
  557. writel(0x0F0000C3, &ccm->CCGR5);
  558. writel(0x000003FF, &ccm->CCGR6);
  559. }
  560. static int mx6q_dcd_table[] = {
  561. 0x020e0798, 0x000C0000,
  562. 0x020e0758, 0x00000000,
  563. 0x020e0588, 0x00000030,
  564. 0x020e0594, 0x00000030,
  565. 0x020e056c, 0x00000030,
  566. 0x020e0578, 0x00000030,
  567. 0x020e074c, 0x00000030,
  568. 0x020e057c, 0x00000030,
  569. 0x020e058c, 0x00000000,
  570. 0x020e059c, 0x00000030,
  571. 0x020e05a0, 0x00000030,
  572. 0x020e078c, 0x00000030,
  573. 0x020e0750, 0x00020000,
  574. 0x020e05a8, 0x00000028,
  575. 0x020e05b0, 0x00000028,
  576. 0x020e0524, 0x00000028,
  577. 0x020e051c, 0x00000028,
  578. 0x020e0518, 0x00000028,
  579. 0x020e050c, 0x00000028,
  580. 0x020e05b8, 0x00000028,
  581. 0x020e05c0, 0x00000028,
  582. 0x020e0774, 0x00020000,
  583. 0x020e0784, 0x00000028,
  584. 0x020e0788, 0x00000028,
  585. 0x020e0794, 0x00000028,
  586. 0x020e079c, 0x00000028,
  587. 0x020e07a0, 0x00000028,
  588. 0x020e07a4, 0x00000028,
  589. 0x020e07a8, 0x00000028,
  590. 0x020e0748, 0x00000028,
  591. 0x020e05ac, 0x00000028,
  592. 0x020e05b4, 0x00000028,
  593. 0x020e0528, 0x00000028,
  594. 0x020e0520, 0x00000028,
  595. 0x020e0514, 0x00000028,
  596. 0x020e0510, 0x00000028,
  597. 0x020e05bc, 0x00000028,
  598. 0x020e05c4, 0x00000028,
  599. 0x021b0800, 0xa1390003,
  600. 0x021b080c, 0x001F001F,
  601. 0x021b0810, 0x001F001F,
  602. 0x021b480c, 0x001F001F,
  603. 0x021b4810, 0x001F001F,
  604. 0x021b083c, 0x43260335,
  605. 0x021b0840, 0x031A030B,
  606. 0x021b483c, 0x4323033B,
  607. 0x021b4840, 0x0323026F,
  608. 0x021b0848, 0x483D4545,
  609. 0x021b4848, 0x44433E48,
  610. 0x021b0850, 0x41444840,
  611. 0x021b4850, 0x4835483E,
  612. 0x021b081c, 0x33333333,
  613. 0x021b0820, 0x33333333,
  614. 0x021b0824, 0x33333333,
  615. 0x021b0828, 0x33333333,
  616. 0x021b481c, 0x33333333,
  617. 0x021b4820, 0x33333333,
  618. 0x021b4824, 0x33333333,
  619. 0x021b4828, 0x33333333,
  620. 0x021b08b8, 0x00000800,
  621. 0x021b48b8, 0x00000800,
  622. 0x021b0004, 0x00020036,
  623. 0x021b0008, 0x09444040,
  624. 0x021b000c, 0x8A8F7955,
  625. 0x021b0010, 0xFF328F64,
  626. 0x021b0014, 0x01FF00DB,
  627. 0x021b0018, 0x00001740,
  628. 0x021b001c, 0x00008000,
  629. 0x021b002c, 0x000026d2,
  630. 0x021b0030, 0x008F1023,
  631. 0x021b0040, 0x00000047,
  632. 0x021b0000, 0x841A0000,
  633. 0x021b001c, 0x04088032,
  634. 0x021b001c, 0x00008033,
  635. 0x021b001c, 0x00048031,
  636. 0x021b001c, 0x09408030,
  637. 0x021b001c, 0x04008040,
  638. 0x021b0020, 0x00005800,
  639. 0x021b0818, 0x00011117,
  640. 0x021b4818, 0x00011117,
  641. 0x021b0004, 0x00025576,
  642. 0x021b0404, 0x00011006,
  643. 0x021b001c, 0x00000000,
  644. 0x020c4068, 0x00C03F3F,
  645. 0x020c406c, 0x0030FC03,
  646. 0x020c4070, 0x0FFFC000,
  647. 0x020c4074, 0x3FF00000,
  648. 0x020c4078, 0xFFFFF300,
  649. 0x020c407c, 0x0F0000F3,
  650. 0x020c4080, 0x00000FFF,
  651. 0x020e0010, 0xF00000CF,
  652. 0x020e0018, 0x007F007F,
  653. 0x020e001c, 0x007F007F,
  654. };
  655. static int mx6qp_dcd_table[] = {
  656. 0x020e0798, 0x000C0000,
  657. 0x020e0758, 0x00000000,
  658. 0x020e0588, 0x00000030,
  659. 0x020e0594, 0x00000030,
  660. 0x020e056c, 0x00000030,
  661. 0x020e0578, 0x00000030,
  662. 0x020e074c, 0x00000030,
  663. 0x020e057c, 0x00000030,
  664. 0x020e058c, 0x00000000,
  665. 0x020e059c, 0x00000030,
  666. 0x020e05a0, 0x00000030,
  667. 0x020e078c, 0x00000030,
  668. 0x020e0750, 0x00020000,
  669. 0x020e05a8, 0x00000030,
  670. 0x020e05b0, 0x00000030,
  671. 0x020e0524, 0x00000030,
  672. 0x020e051c, 0x00000030,
  673. 0x020e0518, 0x00000030,
  674. 0x020e050c, 0x00000030,
  675. 0x020e05b8, 0x00000030,
  676. 0x020e05c0, 0x00000030,
  677. 0x020e0774, 0x00020000,
  678. 0x020e0784, 0x00000030,
  679. 0x020e0788, 0x00000030,
  680. 0x020e0794, 0x00000030,
  681. 0x020e079c, 0x00000030,
  682. 0x020e07a0, 0x00000030,
  683. 0x020e07a4, 0x00000030,
  684. 0x020e07a8, 0x00000030,
  685. 0x020e0748, 0x00000030,
  686. 0x020e05ac, 0x00000030,
  687. 0x020e05b4, 0x00000030,
  688. 0x020e0528, 0x00000030,
  689. 0x020e0520, 0x00000030,
  690. 0x020e0514, 0x00000030,
  691. 0x020e0510, 0x00000030,
  692. 0x020e05bc, 0x00000030,
  693. 0x020e05c4, 0x00000030,
  694. 0x021b0800, 0xa1390003,
  695. 0x021b080c, 0x001b001e,
  696. 0x021b0810, 0x002e0029,
  697. 0x021b480c, 0x001b002a,
  698. 0x021b4810, 0x0019002c,
  699. 0x021b083c, 0x43240334,
  700. 0x021b0840, 0x0324031a,
  701. 0x021b483c, 0x43340344,
  702. 0x021b4840, 0x03280276,
  703. 0x021b0848, 0x44383A3E,
  704. 0x021b4848, 0x3C3C3846,
  705. 0x021b0850, 0x2e303230,
  706. 0x021b4850, 0x38283E34,
  707. 0x021b081c, 0x33333333,
  708. 0x021b0820, 0x33333333,
  709. 0x021b0824, 0x33333333,
  710. 0x021b0828, 0x33333333,
  711. 0x021b481c, 0x33333333,
  712. 0x021b4820, 0x33333333,
  713. 0x021b4824, 0x33333333,
  714. 0x021b4828, 0x33333333,
  715. 0x021b08c0, 0x24912492,
  716. 0x021b48c0, 0x24912492,
  717. 0x021b08b8, 0x00000800,
  718. 0x021b48b8, 0x00000800,
  719. 0x021b0004, 0x00020036,
  720. 0x021b0008, 0x09444040,
  721. 0x021b000c, 0x898E7955,
  722. 0x021b0010, 0xFF328F64,
  723. 0x021b0014, 0x01FF00DB,
  724. 0x021b0018, 0x00001740,
  725. 0x021b001c, 0x00008000,
  726. 0x021b002c, 0x000026d2,
  727. 0x021b0030, 0x008E1023,
  728. 0x021b0040, 0x00000047,
  729. 0x021b0400, 0x14420000,
  730. 0x021b0000, 0x841A0000,
  731. 0x00bb0008, 0x00000004,
  732. 0x00bb000c, 0x2891E41A,
  733. 0x00bb0038, 0x00000564,
  734. 0x00bb0014, 0x00000040,
  735. 0x00bb0028, 0x00000020,
  736. 0x00bb002c, 0x00000020,
  737. 0x021b001c, 0x04088032,
  738. 0x021b001c, 0x00008033,
  739. 0x021b001c, 0x00048031,
  740. 0x021b001c, 0x09408030,
  741. 0x021b001c, 0x04008040,
  742. 0x021b0020, 0x00005800,
  743. 0x021b0818, 0x00011117,
  744. 0x021b4818, 0x00011117,
  745. 0x021b0004, 0x00025576,
  746. 0x021b0404, 0x00011006,
  747. 0x021b001c, 0x00000000,
  748. 0x020c4068, 0x00C03F3F,
  749. 0x020c406c, 0x0030FC03,
  750. 0x020c4070, 0x0FFFC000,
  751. 0x020c4074, 0x3FF00000,
  752. 0x020c4078, 0xFFFFF300,
  753. 0x020c407c, 0x0F0000F3,
  754. 0x020c4080, 0x00000FFF,
  755. 0x020e0010, 0xF00000CF,
  756. 0x020e0018, 0x77177717,
  757. 0x020e001c, 0x77177717,
  758. };
  759. static int mx6dl_dcd_table[] = {
  760. 0x020e0774, 0x000C0000,
  761. 0x020e0754, 0x00000000,
  762. 0x020e04ac, 0x00000030,
  763. 0x020e04b0, 0x00000030,
  764. 0x020e0464, 0x00000030,
  765. 0x020e0490, 0x00000030,
  766. 0x020e074c, 0x00000030,
  767. 0x020e0494, 0x00000030,
  768. 0x020e04a0, 0x00000000,
  769. 0x020e04b4, 0x00000030,
  770. 0x020e04b8, 0x00000030,
  771. 0x020e076c, 0x00000030,
  772. 0x020e0750, 0x00020000,
  773. 0x020e04bc, 0x00000028,
  774. 0x020e04c0, 0x00000028,
  775. 0x020e04c4, 0x00000028,
  776. 0x020e04c8, 0x00000028,
  777. 0x020e04cc, 0x00000028,
  778. 0x020e04d0, 0x00000028,
  779. 0x020e04d4, 0x00000028,
  780. 0x020e04d8, 0x00000028,
  781. 0x020e0760, 0x00020000,
  782. 0x020e0764, 0x00000028,
  783. 0x020e0770, 0x00000028,
  784. 0x020e0778, 0x00000028,
  785. 0x020e077c, 0x00000028,
  786. 0x020e0780, 0x00000028,
  787. 0x020e0784, 0x00000028,
  788. 0x020e078c, 0x00000028,
  789. 0x020e0748, 0x00000028,
  790. 0x020e0470, 0x00000028,
  791. 0x020e0474, 0x00000028,
  792. 0x020e0478, 0x00000028,
  793. 0x020e047c, 0x00000028,
  794. 0x020e0480, 0x00000028,
  795. 0x020e0484, 0x00000028,
  796. 0x020e0488, 0x00000028,
  797. 0x020e048c, 0x00000028,
  798. 0x021b0800, 0xa1390003,
  799. 0x021b080c, 0x001F001F,
  800. 0x021b0810, 0x001F001F,
  801. 0x021b480c, 0x001F001F,
  802. 0x021b4810, 0x001F001F,
  803. 0x021b083c, 0x42190217,
  804. 0x021b0840, 0x017B017B,
  805. 0x021b483c, 0x4176017B,
  806. 0x021b4840, 0x015F016C,
  807. 0x021b0848, 0x4C4C4D4C,
  808. 0x021b4848, 0x4A4D4C48,
  809. 0x021b0850, 0x3F3F3F40,
  810. 0x021b4850, 0x3538382E,
  811. 0x021b081c, 0x33333333,
  812. 0x021b0820, 0x33333333,
  813. 0x021b0824, 0x33333333,
  814. 0x021b0828, 0x33333333,
  815. 0x021b481c, 0x33333333,
  816. 0x021b4820, 0x33333333,
  817. 0x021b4824, 0x33333333,
  818. 0x021b4828, 0x33333333,
  819. 0x021b08b8, 0x00000800,
  820. 0x021b48b8, 0x00000800,
  821. 0x021b0004, 0x00020025,
  822. 0x021b0008, 0x00333030,
  823. 0x021b000c, 0x676B5313,
  824. 0x021b0010, 0xB66E8B63,
  825. 0x021b0014, 0x01FF00DB,
  826. 0x021b0018, 0x00001740,
  827. 0x021b001c, 0x00008000,
  828. 0x021b002c, 0x000026d2,
  829. 0x021b0030, 0x006B1023,
  830. 0x021b0040, 0x00000047,
  831. 0x021b0000, 0x841A0000,
  832. 0x021b001c, 0x04008032,
  833. 0x021b001c, 0x00008033,
  834. 0x021b001c, 0x00048031,
  835. 0x021b001c, 0x05208030,
  836. 0x021b001c, 0x04008040,
  837. 0x021b0020, 0x00005800,
  838. 0x021b0818, 0x00011117,
  839. 0x021b4818, 0x00011117,
  840. 0x021b0004, 0x00025565,
  841. 0x021b0404, 0x00011006,
  842. 0x021b001c, 0x00000000,
  843. 0x020c4068, 0x00C03F3F,
  844. 0x020c406c, 0x0030FC03,
  845. 0x020c4070, 0x0FFFC000,
  846. 0x020c4074, 0x3FF00000,
  847. 0x020c4078, 0xFFFFF300,
  848. 0x020c407c, 0x0F0000C3,
  849. 0x020c4080, 0x00000FFF,
  850. 0x020e0010, 0xF00000CF,
  851. 0x020e0018, 0x007F007F,
  852. 0x020e001c, 0x007F007F,
  853. };
  854. static void ddr_init(int *table, int size)
  855. {
  856. int i;
  857. for (i = 0; i < size / 2 ; i++)
  858. writel(table[2 * i + 1], table[2 * i]);
  859. }
  860. static void spl_dram_init(void)
  861. {
  862. if (is_mx6dq())
  863. ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
  864. else if (is_mx6dqp())
  865. ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));
  866. else if (is_mx6sdl())
  867. ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
  868. }
  869. void board_init_f(ulong dummy)
  870. {
  871. /* DDR initialization */
  872. spl_dram_init();
  873. /* setup AIPS and disable watchdog */
  874. arch_cpu_init();
  875. ccgr_init();
  876. gpr_init();
  877. /* iomux and setup of i2c */
  878. board_early_init_f();
  879. /* setup GP timer */
  880. timer_init();
  881. /* UART clocks enabled and gd valid - init serial console */
  882. preloader_console_init();
  883. /* Clear the BSS. */
  884. memset(__bss_start, 0, __bss_end - __bss_start);
  885. /* load/boot image from boot device */
  886. board_init_r(NULL, 0);
  887. }
  888. #endif
  889. #ifdef CONFIG_SPL_LOAD_FIT
  890. int board_fit_config_name_match(const char *name)
  891. {
  892. if (is_mx6dq()) {
  893. if (!strcmp(name, "imx6q-sabreauto"))
  894. return 0;
  895. } else if (is_mx6dqp()) {
  896. if (!strcmp(name, "imx6qp-sabreauto"))
  897. return 0;
  898. } else if (is_mx6dl()) {
  899. if (!strcmp(name, "imx6dl-sabreauto"))
  900. return 0;
  901. }
  902. return -1;
  903. }
  904. #endif