spl.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Nelson Integration, LLC
  4. * Author: Eric Nelson <eric@nelint.com>
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <init.h>
  9. #include <asm/global_data.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/iomux.h>
  12. #include <asm/arch/clock.h>
  13. #include <asm/arch/crm_regs.h>
  14. #include <asm/arch/mx6-ddr.h>
  15. #include <asm/arch/mx6-pins.h>
  16. #include <asm/arch/sys_proto.h>
  17. #include <spl.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  20. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  21. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  22. static iomux_v3_cfg_t const uart_pads[] = {
  23. #ifdef CONFIG_UART2_EIM_D26_27
  24. IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  25. IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  26. #elif defined(CONFIG_UART1_CSI0_DAT10_11)
  27. IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  28. IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  29. #elif defined(CONFIG_UART1_SD3_DAT6_7)
  30. IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  31. IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  32. #elif defined(CONFIG_UART1_UART1)
  33. MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  34. MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  35. #else
  36. #error select UART console pads
  37. #endif
  38. };
  39. #ifdef CONFIG_DDR3
  40. #define GRP_DDRTYPE 0x000C0000
  41. #else
  42. #define GRP_DDRTYPE 0x00080000
  43. #endif
  44. /* all existing designs have this disabled */
  45. #define DDR_PKE 0
  46. /* use Kconfig for ODT and DRIVE_STRENGTH */
  47. #define DDR_ODT \
  48. (CONFIG_DDR_ODT << 8)
  49. #define DRAM_DRIVE_STRENGTH \
  50. (CONFIG_DRAM_DRIVE_STRENGTH << 3)
  51. /* configure MX6Q/DUAL mmdc DDR io registers */
  52. static struct mx6dq_iomux_ddr_regs const mx6dq_ddr_ioregs = {
  53. /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
  54. .dram_sdclk_0 = DDR_ODT + DRAM_DRIVE_STRENGTH,
  55. .dram_sdclk_1 = DDR_ODT + DRAM_DRIVE_STRENGTH,
  56. .dram_cas = DDR_ODT + DRAM_DRIVE_STRENGTH,
  57. .dram_ras = DDR_ODT + DRAM_DRIVE_STRENGTH,
  58. .dram_reset = DDR_ODT + DRAM_DRIVE_STRENGTH,
  59. /* SDCKE[0:1]: 100k pull-up */
  60. .dram_sdcke0 = 0x00003000,
  61. .dram_sdcke1 = 0x00003000,
  62. /* SDBA2: pull-up disabled */
  63. .dram_sdba2 = 0x00000000,
  64. /* SDODT[0:1]: 100k pull-up, 40 ohm */
  65. .dram_sdodt0 = 0x00003000 + DRAM_DRIVE_STRENGTH,
  66. .dram_sdodt1 = 0x00003000 + DRAM_DRIVE_STRENGTH,
  67. /* SDQS[0:7]: Differential input, 40 ohm */
  68. .dram_sdqs0 = DRAM_DRIVE_STRENGTH,
  69. .dram_sdqs1 = DRAM_DRIVE_STRENGTH,
  70. .dram_sdqs2 = DRAM_DRIVE_STRENGTH,
  71. .dram_sdqs3 = DRAM_DRIVE_STRENGTH,
  72. .dram_sdqs4 = DRAM_DRIVE_STRENGTH,
  73. .dram_sdqs5 = DRAM_DRIVE_STRENGTH,
  74. .dram_sdqs6 = DRAM_DRIVE_STRENGTH,
  75. .dram_sdqs7 = DRAM_DRIVE_STRENGTH,
  76. /* DQM[0:7]: Differential input, 40 ohm */
  77. .dram_dqm0 = DDR_ODT + DRAM_DRIVE_STRENGTH,
  78. .dram_dqm1 = DDR_ODT + DRAM_DRIVE_STRENGTH,
  79. .dram_dqm2 = DDR_ODT + DRAM_DRIVE_STRENGTH,
  80. .dram_dqm3 = DDR_ODT + DRAM_DRIVE_STRENGTH,
  81. .dram_dqm4 = DDR_ODT + DRAM_DRIVE_STRENGTH,
  82. .dram_dqm5 = DDR_ODT + DRAM_DRIVE_STRENGTH,
  83. .dram_dqm6 = DDR_ODT + DRAM_DRIVE_STRENGTH,
  84. .dram_dqm7 = DDR_ODT + DRAM_DRIVE_STRENGTH,
  85. };
  86. /* configure MX6Q/DUAL mmdc GRP io registers */
  87. static struct mx6dq_iomux_grp_regs const mx6dq_grp_ioregs = {
  88. /* DDR3 */
  89. .grp_ddr_type = GRP_DDRTYPE,
  90. .grp_ddrmode_ctl = DDR_ODT,
  91. /* disable DDR pullups */
  92. .grp_ddrpke = DDR_PKE,
  93. /* ADDR[00:16], SDBA[0:1]: 40 ohm */
  94. .grp_addds = DRAM_DRIVE_STRENGTH,
  95. /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
  96. .grp_ctlds = DRAM_DRIVE_STRENGTH,
  97. /* DATA[00:63]: Differential input, 40 ohm */
  98. .grp_ddrmode = DDR_ODT,
  99. .grp_b0ds = DRAM_DRIVE_STRENGTH,
  100. .grp_b1ds = DRAM_DRIVE_STRENGTH,
  101. .grp_b2ds = DRAM_DRIVE_STRENGTH,
  102. .grp_b3ds = DRAM_DRIVE_STRENGTH,
  103. .grp_b4ds = DRAM_DRIVE_STRENGTH,
  104. .grp_b5ds = DRAM_DRIVE_STRENGTH,
  105. .grp_b6ds = DRAM_DRIVE_STRENGTH,
  106. .grp_b7ds = DRAM_DRIVE_STRENGTH,
  107. };
  108. static struct mx6sdl_iomux_ddr_regs const mx6sdl_ddr_ioregs = {
  109. /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
  110. .dram_sdclk_0 = DDR_ODT + DRAM_DRIVE_STRENGTH,
  111. .dram_sdclk_1 = DDR_ODT + DRAM_DRIVE_STRENGTH,
  112. .dram_cas = DDR_ODT + DRAM_DRIVE_STRENGTH,
  113. .dram_ras = DDR_ODT + DRAM_DRIVE_STRENGTH,
  114. .dram_reset = DDR_ODT + DRAM_DRIVE_STRENGTH,
  115. /* SDCKE[0:1]: 100k pull-up */
  116. .dram_sdcke0 = 0x00003000,
  117. .dram_sdcke1 = 0x00003000,
  118. /* SDBA2: pull-up disabled */
  119. .dram_sdba2 = 0x00000000,
  120. /* SDODT[0:1]: 100k pull-up, 40 ohm */
  121. .dram_sdodt0 = 0x00003000 + DRAM_DRIVE_STRENGTH,
  122. .dram_sdodt1 = 0x00003000 + DRAM_DRIVE_STRENGTH,
  123. /* SDQS[0:7]: Differential input, 40 ohm */
  124. .dram_sdqs0 = DRAM_DRIVE_STRENGTH,
  125. .dram_sdqs1 = DRAM_DRIVE_STRENGTH,
  126. .dram_sdqs2 = DRAM_DRIVE_STRENGTH,
  127. .dram_sdqs3 = DRAM_DRIVE_STRENGTH,
  128. .dram_sdqs4 = DRAM_DRIVE_STRENGTH,
  129. .dram_sdqs5 = DRAM_DRIVE_STRENGTH,
  130. .dram_sdqs6 = DRAM_DRIVE_STRENGTH,
  131. .dram_sdqs7 = DRAM_DRIVE_STRENGTH,
  132. /* DQM[0:7]: Differential input, 40 ohm */
  133. .dram_dqm0 = DDR_ODT + DRAM_DRIVE_STRENGTH,
  134. .dram_dqm1 = DDR_ODT + DRAM_DRIVE_STRENGTH,
  135. .dram_dqm2 = DDR_ODT + DRAM_DRIVE_STRENGTH,
  136. .dram_dqm3 = DDR_ODT + DRAM_DRIVE_STRENGTH,
  137. .dram_dqm4 = DDR_ODT + DRAM_DRIVE_STRENGTH,
  138. .dram_dqm5 = DDR_ODT + DRAM_DRIVE_STRENGTH,
  139. .dram_dqm6 = DDR_ODT + DRAM_DRIVE_STRENGTH,
  140. .dram_dqm7 = DDR_ODT + DRAM_DRIVE_STRENGTH,
  141. };
  142. /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
  143. static struct mx6sdl_iomux_grp_regs const mx6sdl_grp_ioregs = {
  144. /* DDR3 */
  145. .grp_ddr_type = GRP_DDRTYPE,
  146. /* SDQS[0:7]: Differential input, 40 ohm */
  147. .grp_ddrmode_ctl = DDR_ODT,
  148. /* disable DDR pullups */
  149. .grp_ddrpke = DDR_PKE,
  150. /* ADDR[00:16], SDBA[0:1]: 40 ohm */
  151. .grp_addds = DRAM_DRIVE_STRENGTH,
  152. /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
  153. .grp_ctlds = DRAM_DRIVE_STRENGTH,
  154. /* DATA[00:63]: Differential input, 40 ohm */
  155. .grp_ddrmode = DDR_ODT,
  156. .grp_b0ds = DRAM_DRIVE_STRENGTH,
  157. .grp_b1ds = DRAM_DRIVE_STRENGTH,
  158. .grp_b2ds = DRAM_DRIVE_STRENGTH,
  159. .grp_b3ds = DRAM_DRIVE_STRENGTH,
  160. .grp_b4ds = DRAM_DRIVE_STRENGTH,
  161. .grp_b5ds = DRAM_DRIVE_STRENGTH,
  162. .grp_b6ds = DRAM_DRIVE_STRENGTH,
  163. .grp_b7ds = DRAM_DRIVE_STRENGTH,
  164. };
  165. const struct mx6sl_iomux_ddr_regs mx6sl_ddr_ioregs = {
  166. .dram_sdqs0 = DRAM_DRIVE_STRENGTH,
  167. .dram_sdqs1 = DRAM_DRIVE_STRENGTH,
  168. .dram_sdqs2 = DRAM_DRIVE_STRENGTH,
  169. .dram_sdqs3 = DRAM_DRIVE_STRENGTH,
  170. .dram_dqm0 = DRAM_DRIVE_STRENGTH,
  171. .dram_dqm1 = DRAM_DRIVE_STRENGTH,
  172. .dram_dqm2 = DRAM_DRIVE_STRENGTH,
  173. .dram_dqm3 = DRAM_DRIVE_STRENGTH,
  174. .dram_cas = DRAM_DRIVE_STRENGTH,
  175. .dram_ras = DRAM_DRIVE_STRENGTH,
  176. .dram_sdclk_0 = DRAM_DRIVE_STRENGTH,
  177. .dram_reset = DRAM_DRIVE_STRENGTH,
  178. .dram_sdba2 = 0x00020000,
  179. .dram_odt0 = 0x00030000 + DRAM_DRIVE_STRENGTH,
  180. .dram_odt1 = 0x00030000 + DRAM_DRIVE_STRENGTH,
  181. };
  182. const struct mx6sl_iomux_grp_regs mx6sl_grp_ioregs = {
  183. .grp_b0ds = DRAM_DRIVE_STRENGTH,
  184. .grp_b1ds = DRAM_DRIVE_STRENGTH,
  185. .grp_b2ds = DRAM_DRIVE_STRENGTH,
  186. .grp_b3ds = DRAM_DRIVE_STRENGTH,
  187. .grp_addds = DRAM_DRIVE_STRENGTH,
  188. .grp_ctlds = DRAM_DRIVE_STRENGTH,
  189. .grp_ddrmode_ctl = DDR_ODT,
  190. .grp_ddrpke = DDR_PKE,
  191. .grp_ddrmode = DDR_ODT,
  192. .grp_ddr_type = GRP_DDRTYPE,
  193. };
  194. static struct mx6_ddr_sysinfo const sysinfo = {
  195. /* width of data bus:0=16,1=32,2=64 */
  196. #if CONFIG_DDRWIDTH == 32
  197. .dsize = 1,
  198. #elif CONFIG_DDRWIDTH == 64
  199. .dsize = 2,
  200. #else
  201. #error missing CONFIG_DDRWIDTH
  202. #endif
  203. /* config for full 4GB range so that get_mem_size() works */
  204. .cs_density = 32, /* 32Gb per CS */
  205. /* # of chip selects */
  206. .ncs = CONFIG_DDRCS,
  207. .cs1_mirror = 0,
  208. .bi_on = 1, /* Bank interleaving enabled */
  209. .rtt_nom = CONFIG_RTT_NOM,
  210. .rtt_wr = CONFIG_RTT_WR,
  211. .ralat = CONFIG_RALAT, /* Read additional latency */
  212. .walat = CONFIG_WALAT, /* Write additional latency */
  213. .mif3_mode = 3, /* Command prediction working mode */
  214. #ifdef CONFIG_DDR3
  215. .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
  216. .sde_to_rst = 0x10, /* JEDEC value for LPDDR2 - 200us */
  217. .pd_fast_exit = 0, /* immaterial for calibration */
  218. .ddr_type = DDR_TYPE_DDR3,
  219. #else
  220. .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
  221. .sde_to_rst = 0, /* LPDDR2 does not need this field */
  222. .pd_fast_exit = 0, /* immaterial for calibration */
  223. .ddr_type = DDR_TYPE_LPDDR2,
  224. #endif
  225. .refsel = CONFIG_REFSEL,
  226. .refr = CONFIG_REFR,
  227. };
  228. #ifdef CONFIG_MT41K512M16TNA
  229. /* Micron MT41K512M16TNA-125 */
  230. static struct mx6_ddr3_cfg const ddrtype = {
  231. .mem_speed = 1600,
  232. .density = 8,
  233. .width = 16,
  234. .banks = 8,
  235. .rowaddr = 15,
  236. .coladdr = 10,
  237. .pagesz = 1,
  238. .trcd = 1375,
  239. .trcmin = 5062,
  240. .trasmin = 3750,
  241. };
  242. #elif defined(CONFIG_MT41K128M16JT)
  243. /* Micron MT41K128M16JT-125 */
  244. static struct mx6_ddr3_cfg const ddrtype = {
  245. .mem_speed = 1600,
  246. .density = 2,
  247. .width = 16,
  248. .banks = 8,
  249. .rowaddr = 14,
  250. .coladdr = 10,
  251. .pagesz = 2,
  252. .trcd = 1375,
  253. .trcmin = 4875,
  254. .trasmin = 3500,
  255. };
  256. #elif defined(CONFIG_H5TQ4G63AFR)
  257. /* Hynix H5TQ4G63AFR */
  258. static struct mx6_ddr3_cfg const ddrtype = {
  259. .mem_speed = 1600,
  260. .density = 4,
  261. .width = 16,
  262. .banks = 8,
  263. .rowaddr = 15,
  264. .coladdr = 10,
  265. .pagesz = 2,
  266. .trcd = 1375,
  267. .trcmin = 4875,
  268. .trasmin = 3500,
  269. };
  270. #elif defined CONFIG_H5TQ2G63DFR
  271. /* Hynix H5TQ2G63DFR */
  272. static struct mx6_ddr3_cfg const ddrtype = {
  273. .mem_speed = 1333,
  274. .density = 2,
  275. .width = 16,
  276. .banks = 8,
  277. .rowaddr = 14,
  278. .coladdr = 10,
  279. .pagesz = 2,
  280. .trcd = 1350,
  281. .trcmin = 4950,
  282. .trasmin = 3600,
  283. };
  284. #elif defined(CONFIG_MT42L256M32D2LG)
  285. /* Micron MT42L256M32D2LG */
  286. static struct mx6_lpddr2_cfg ddrtype = {
  287. .mem_speed = 800,
  288. .density = 4,
  289. .width = 32,
  290. .banks = 8,
  291. .rowaddr = 14,
  292. .coladdr = 10,
  293. .trcd_lp = 2000,
  294. .trppb_lp = 2000,
  295. .trpab_lp = 2250,
  296. .trasmin = 4200,
  297. };
  298. #elif defined(CONFIG_MT29PZZZ4D4BKESK)
  299. /* Micron MT29PZZZ4D4BKESK */
  300. static struct mx6_lpddr2_cfg ddrtype = {
  301. .mem_speed = 800,
  302. .density = 4,
  303. .width = 32,
  304. .banks = 8,
  305. .rowaddr = 14,
  306. .coladdr = 10,
  307. .trcd_lp = 2000,
  308. .trppb_lp = 2000,
  309. .trpab_lp = 2250,
  310. .trasmin = 4200,
  311. };
  312. #else
  313. #error please select DDR type using menuconfig
  314. #endif
  315. static void ccgr_init(void)
  316. {
  317. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  318. /* FIXME: these should probably be checked, especially
  319. * for i.MX6SL, UL, ULL
  320. */
  321. writel(0x00C03F3F, &ccm->CCGR0);
  322. writel(0x0030FC03, &ccm->CCGR1);
  323. writel(0x0FFFC000, &ccm->CCGR2);
  324. writel(0x3FF00000, &ccm->CCGR3);
  325. writel(0x00FFF300, &ccm->CCGR4);
  326. writel(0x0F0000C3, &ccm->CCGR5);
  327. writel(0x000003FF, &ccm->CCGR6);
  328. }
  329. static void display_calibration(struct mx6_mmdc_calibration *calib)
  330. {
  331. printf(".p0_mpdgctrl0\t= 0x%08X\n", calib->p0_mpdgctrl0);
  332. printf(".p0_mpdgctrl1\t= 0x%08X\n", calib->p0_mpdgctrl1);
  333. printf(".p0_mprddlctl\t= 0x%08X\n", calib->p0_mprddlctl);
  334. printf(".p0_mpwrdlctl\t= 0x%08X\n", calib->p0_mpwrdlctl);
  335. printf(".p0_mpwldectrl0\t= 0x%08X\n", calib->p0_mpwldectrl0);
  336. printf(".p0_mpwldectrl1\t= 0x%08X\n", calib->p0_mpwldectrl1);
  337. if (sysinfo.dsize == 2) {
  338. printf(".p1_mpdgctrl0\t= 0x%08X\n", calib->p1_mpdgctrl0);
  339. printf(".p1_mpdgctrl1\t= 0x%08X\n", calib->p1_mpdgctrl1);
  340. printf(".p1_mprddlctl\t= 0x%08X\n", calib->p1_mprddlctl);
  341. printf(".p1_mpwrdlctl\t= 0x%08X\n", calib->p1_mpwrdlctl);
  342. printf(".p1_mpwldectrl0\t= 0x%08X\n", calib->p1_mpwldectrl0);
  343. printf(".p1_mpwldectrl1\t= 0x%08X\n", calib->p1_mpwldectrl1);
  344. }
  345. #ifdef CONFIG_IMXIMAGE_OUTPUT
  346. printf("DATA 4 MX6_MMDC_P0_MPDGCTRL0\t= 0x%08X\n", calib->p0_mpdgctrl0);
  347. printf("DATA 4 MX6_MMDC_P0_MPDGCTRL1\t= 0x%08X\n", calib->p0_mpdgctrl1);
  348. printf("DATA 4 MX6_MMDC_P0_MPRDDLCTL\t= 0x%08X\n", calib->p0_mprddlctl);
  349. printf("DATA 4 MX6_MMDC_P0_MPWRDLCTL\t= 0x%08X\n", calib->p0_mpwrdlctl);
  350. printf("DATA 4 MX6_MMDC_P0_MPWLDECTRL0\t= 0x%08X\n",
  351. calib->p0_mpwldectrl0);
  352. printf("DATA 4 MX6_MMDC_P0_MPWLDECTRL1\t= 0x%08X\n",
  353. calib->p0_mpwldectrl1);
  354. if (sysinfo.dsize == 2) {
  355. printf("DATA 4 MX6_MMDC_P1_MPDGCTRL0\t= 0x%08X\n",
  356. calib->p1_mpdgctrl0);
  357. printf("DATA 4 MX6_MMDC_P1_MPDGCTRL1\t= 0x%08X\n",
  358. calib->p1_mpdgctrl1);
  359. printf("DATA 4 MX6_MMDC_P1_MPRDDLCTL\t= 0x%08X\n",
  360. calib->p1_mprddlctl);
  361. printf("DATA 4 MX6_MMDC_P1_MPWRDLCTL\t= 0x%08X\n",
  362. calib->p1_mpwrdlctl);
  363. printf("DATA 4 MX6_MMDC_P1_MPWLDECTRL0\t= 0x%08X\n",
  364. calib->p1_mpwldectrl0);
  365. printf("DATA 4 MX6_MMDC_P1_MPWLDECTRL1\t= 0x%08X\n",
  366. calib->p1_mpwldectrl1);
  367. }
  368. #endif
  369. }
  370. /*
  371. * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
  372. * - we have a stack and a place to store GD, both in SRAM
  373. * - no variable global data is available
  374. */
  375. void board_init_f(ulong dummy)
  376. {
  377. int errs;
  378. struct mx6_mmdc_calibration calibration = {0};
  379. memset((void *)gd, 0, sizeof(struct global_data));
  380. /* write leveling calibration defaults */
  381. calibration.p0_mpwrdlctl = 0x40404040;
  382. calibration.p1_mpwrdlctl = 0x40404040;
  383. /* setup AIPS and disable watchdog */
  384. arch_cpu_init();
  385. ccgr_init();
  386. SETUP_IOMUX_PADS(uart_pads);
  387. /* setup GP timer */
  388. timer_init();
  389. /* UART clocks enabled and gd valid - init serial console */
  390. preloader_console_init();
  391. if (sysinfo.dsize != 1) {
  392. if (is_cpu_type(MXC_CPU_MX6SX) ||
  393. is_cpu_type(MXC_CPU_MX6UL) ||
  394. is_cpu_type(MXC_CPU_MX6ULL) ||
  395. is_cpu_type(MXC_CPU_MX6SL)) {
  396. printf("cpu type 0x%x doesn't support 64-bit bus\n",
  397. get_cpu_type());
  398. reset_cpu();
  399. }
  400. }
  401. #ifdef CONFIG_MX6SL
  402. mx6sl_dram_iocfg(CONFIG_DDRWIDTH, &mx6sl_ddr_ioregs,
  403. &mx6sl_grp_ioregs);
  404. #else
  405. if (is_cpu_type(MXC_CPU_MX6Q)) {
  406. mx6dq_dram_iocfg(CONFIG_DDRWIDTH, &mx6dq_ddr_ioregs,
  407. &mx6dq_grp_ioregs);
  408. } else {
  409. mx6sdl_dram_iocfg(CONFIG_DDRWIDTH, &mx6sdl_ddr_ioregs,
  410. &mx6sdl_grp_ioregs);
  411. }
  412. #endif
  413. mx6_dram_cfg(&sysinfo, &calibration, &ddrtype);
  414. errs = mmdc_do_write_level_calibration(&sysinfo);
  415. if (errs) {
  416. printf("error %d from write level calibration\n", errs);
  417. } else {
  418. errs = mmdc_do_dqs_calibration(&sysinfo);
  419. if (errs) {
  420. printf("error %d from dqs calibration\n", errs);
  421. } else {
  422. printf("completed successfully\n");
  423. mmdc_read_calibration(&sysinfo, &calibration);
  424. display_calibration(&calibration);
  425. }
  426. }
  427. }