Kconfig 4.8 KB

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  1. if TARGET_MX6MEMCAL
  2. config SYS_BOARD
  3. default "mx6memcal"
  4. config SYS_VENDOR
  5. default "freescale"
  6. config SYS_CONFIG_NAME
  7. default "mx6memcal"
  8. menu "mx6memcal specifics"
  9. choice
  10. prompt "Serial console"
  11. help
  12. Either UART1 or UART2 will be used as the console for
  13. displaying the calibration values or errors.
  14. config SERIAL_CONSOLE_UART1
  15. bool "UART1"
  16. help
  17. Select this if your board uses UART1 for its' console.
  18. config SERIAL_CONSOLE_UART2
  19. bool "UART2"
  20. help
  21. Select this if your board uses UART2 for its' console.
  22. endchoice
  23. choice
  24. prompt "UART pads"
  25. help
  26. Select the RX and TX pads used for your serial console.
  27. The choices below reflect the most commonly used options
  28. for your UART.
  29. config UART2_EIM_D26_27
  30. bool "UART2 on EIM_D26/27 (SabreLite, Nitrogen6x)"
  31. depends on SERIAL_CONSOLE_UART2
  32. help
  33. Choose this configuration if you're using pads
  34. EIM_D26 and D27 for a console on UART2.
  35. This is typical for designs that are based on the
  36. NXP SABRELite.
  37. config UART1_CSI0_DAT10_11
  38. bool "UART1 on CSI0_DAT10/11 (Wand, SabreSD)"
  39. depends on SERIAL_CONSOLE_UART1
  40. help
  41. Choose this configuration if you're using pads
  42. CSI0_DAT10 and DAT11 for a console on UART1 as
  43. is done on the i.MX6 Wand board and i.MX6 SabreSD.
  44. config UART1_UART1
  45. bool "UART1 on UART1 (i.MX6SL EVK, WaRP)"
  46. depends on SERIAL_CONSOLE_UART1
  47. help
  48. Choose this configuration if you're using pads
  49. UART1_TXD/RXD for a console on UART1 as is done
  50. on most i.MX6SL designs.
  51. endchoice
  52. config IMXIMAGE_OUTPUT
  53. bool "Include output for imximage .cfg files"
  54. default y
  55. help
  56. Say "Y" if you want output formatted for use in non-SPL
  57. (DCD-style) configuration files.
  58. config DDRWIDTH
  59. int "DDR bus width"
  60. default 64
  61. help
  62. Select either 32 or 64 to reflect the DDR bus width.
  63. config DDRCS
  64. int "DDR chip selects"
  65. default 2
  66. range 1 2
  67. help
  68. Select the number of chip selects used in your board design
  69. choice
  70. prompt "Memory type"
  71. help
  72. Select the type of DDR (DDR3 or LPDDR2) used on your design
  73. config DDR3
  74. bool "DDR3"
  75. help
  76. Select this if your board design uses DDR3.
  77. config LPDDR2
  78. bool "LPDDR2"
  79. help
  80. Select this if your board design uses LPDDR2.
  81. endchoice
  82. choice
  83. prompt "Memory device"
  84. config MT41K512M16TNA
  85. bool "Micron MT41K512M16TNA 512Mx16 (1GiB/chip)"
  86. depends on DDR3
  87. config MT41K128M16JT
  88. bool "Micron MT41K128M16JT 128Mx16 (256 MiB/chip)"
  89. depends on DDR3
  90. config H5TQ4G63AFR
  91. bool "Hynix H5TQ4G63AFR 256Mx16 (512 MiB/chip)"
  92. depends on DDR3
  93. config H5TQ2G63DFR
  94. bool "Hynix H5TQ2G63DFR 128Mx16 (256 MiB/chip)"
  95. depends on DDR3
  96. config MT42L256M32D2LG
  97. bool "Micron MT42L256M32D2LG LPDDR2 256Mx32 (1GiB/chip)"
  98. depends on LPDDR2
  99. config MT29PZZZ4D4BKESK
  100. bool "Micron MT29PZZZ4D4BKESK multi-chip 512MiB LPDDR2/4GiB eMMC"
  101. depends on LPDDR2
  102. endchoice
  103. config DDR_ODT
  104. int "DDR On-die-termination"
  105. default 2
  106. range 0 7
  107. help
  108. Enter the on-die termination value as an index defined for
  109. IOMUX settings for PAD_DRAM_SDCLK0_P and others.
  110. 0 == Disabled
  111. 1 == 120 Ohm
  112. 2 == 60 Ohm
  113. 3 == 40 Ohm
  114. 4 == 30 Ohm
  115. 5 == 24 Ohm
  116. 6 == 20 Ohm
  117. 7 == 17 Ohm
  118. Value will be applied to all clock and data lines
  119. config DRAM_DRIVE_STRENGTH
  120. int "DRAM Drive strength"
  121. default 6
  122. range 0 7
  123. help
  124. Enter drive strength as an index defined for IOMUX settings
  125. for GRP_B1DS and others.
  126. 0 == Hi Z
  127. 6 == 40 Ohm (default)
  128. 7 == 34 Ohm
  129. Value will be applied to all clock and data lines
  130. config RTT_NOM
  131. int "RTT_NOM"
  132. default 1
  133. range 1 2
  134. help
  135. Enter the RTT_NOM selector
  136. 1 == RZQ/4 (60ohm)
  137. 2 == RZQ/2 (120ohm)
  138. config RTT_WR
  139. int "RTT_WR"
  140. default 1
  141. range 0 2
  142. help
  143. Enter the RTT_WR selector for MR2
  144. 0 == Dynamic ODT disabled
  145. 1 == RZQ/4 (60ohm)
  146. 2 == RZQ/2 (120ohm)
  147. config RALAT
  148. int "Read additional latency"
  149. default 5
  150. range 0 7
  151. help
  152. Enter a latency in number of cycles. This will be added to
  153. CAS and internal delays for which the MMDC will retrieve the
  154. read data from the internal FIFO.
  155. This is used to compensate for board/chip delays.
  156. config WALAT
  157. int "Write additional latency"
  158. default 0
  159. range 0 7
  160. help
  161. Enter a latency in number of cycles. This will be added to
  162. CAS and internal delays for which the MMDC will retrieve the
  163. read data from the internal FIFO
  164. This is used to compensate for board/chip delays.
  165. config REFSEL
  166. int "Refresh period"
  167. range 0 3
  168. default 1
  169. help
  170. Select the DDR refresh period.
  171. See the description of bitfield REF_SEL in the reference manual
  172. for details.
  173. 0 == disabled
  174. 1 == 32 kHz
  175. 2 == 64 kHz
  176. 3 == fast counter
  177. config REFR
  178. int "Number of refreshes"
  179. range 0 7
  180. default 7
  181. help
  182. This selects the number of refreshes (-1) during each period.
  183. i.e.:
  184. 0 == 1 refresh (tRFC)
  185. 7 == 8 refreshes (tRFC*8)
  186. See the description of MDREF[REFR] in the reference manual for
  187. details.
  188. endmenu
  189. endif