mpc8349emds.c 7.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2006
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. #include <common.h>
  7. #include <fdt_support.h>
  8. #include <init.h>
  9. #include <ioports.h>
  10. #include <mpc83xx.h>
  11. #include <asm/bitops.h>
  12. #include <asm/global_data.h>
  13. #include <asm/mpc8349_pci.h>
  14. #include <i2c.h>
  15. #include <spi.h>
  16. #include <miiphy.h>
  17. #ifdef CONFIG_SYS_FSL_DDR2
  18. #include <fsl_ddr_sdram.h>
  19. #else
  20. #include <spd_sdram.h>
  21. #endif
  22. #include <linux/delay.h>
  23. #if defined(CONFIG_OF_LIBFDT)
  24. #include <linux/libfdt.h>
  25. #endif
  26. DECLARE_GLOBAL_DATA_PTR;
  27. int fixed_sdram(void);
  28. void sdram_init(void);
  29. #if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
  30. void ddr_enable_ecc(unsigned int dram_size);
  31. #endif
  32. int board_early_init_f (void)
  33. {
  34. volatile u8* bcsr = (volatile u8*)CONFIG_SYS_BCSR;
  35. /* Enable flash write */
  36. bcsr[1] &= ~0x01;
  37. #ifdef CONFIG_SYS_USE_MPC834XSYS_USB_PHY
  38. /* Use USB PHY on SYS board */
  39. bcsr[5] |= 0x02;
  40. #endif
  41. return 0;
  42. }
  43. #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
  44. int dram_init(void)
  45. {
  46. volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  47. phys_size_t msize = 0;
  48. if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
  49. return -ENXIO;
  50. /* DDR SDRAM - Main SODIMM */
  51. im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
  52. #if defined(CONFIG_SPD_EEPROM)
  53. #ifndef CONFIG_SYS_FSL_DDR2
  54. msize = spd_sdram() * 1024 * 1024;
  55. #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  56. ddr_enable_ecc(msize);
  57. #endif
  58. #else
  59. msize = fsl_ddr_sdram();
  60. #endif
  61. #else
  62. msize = fixed_sdram() * 1024 * 1024;
  63. #endif
  64. /*
  65. * Initialize SDRAM if it is on local bus.
  66. */
  67. sdram_init();
  68. /* set total bus SDRAM size(bytes) -- DDR */
  69. gd->ram_size = msize;
  70. return 0;
  71. }
  72. #if !defined(CONFIG_SPD_EEPROM)
  73. /*************************************************************************
  74. * fixed sdram init -- doesn't use serial presence detect.
  75. ************************************************************************/
  76. int fixed_sdram(void)
  77. {
  78. volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  79. u32 msize = CONFIG_SYS_DDR_SIZE;
  80. u32 ddr_size = msize << 20; /* DDR size in bytes */
  81. u32 ddr_size_log2 = __ilog2(ddr_size);
  82. im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
  83. im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
  84. #if (CONFIG_SYS_DDR_SIZE != 256)
  85. #warning Currenly any ddr size other than 256 is not supported
  86. #endif
  87. #ifdef CONFIG_DDR_II
  88. im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS;
  89. im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
  90. im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
  91. im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  92. im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
  93. im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
  94. im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
  95. im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
  96. im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
  97. im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
  98. im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
  99. im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
  100. #else
  101. #if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
  102. #warning Chip select bounds is only configurable in 16MB increments
  103. #endif
  104. im->ddr.csbnds[2].csbnds =
  105. ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
  106. (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
  107. CSBNDS_EA_SHIFT) & CSBNDS_EA);
  108. im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
  109. /* currently we use only one CS, so disable the other banks */
  110. im->ddr.cs_config[0] = 0;
  111. im->ddr.cs_config[1] = 0;
  112. im->ddr.cs_config[3] = 0;
  113. im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  114. im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
  115. im->ddr.sdram_cfg =
  116. SDRAM_CFG_SREN
  117. #if defined(CONFIG_DDR_2T_TIMING)
  118. | SDRAM_CFG_2T_EN
  119. #endif
  120. | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
  121. #if defined (CONFIG_DDR_32BIT)
  122. /* for 32-bit mode burst length is 8 */
  123. im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
  124. #endif
  125. im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
  126. im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
  127. #endif
  128. udelay(200);
  129. /* enable DDR controller */
  130. im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
  131. return msize;
  132. }
  133. #endif/*!CONFIG_SYS_SPD_EEPROM*/
  134. int checkboard (void)
  135. {
  136. /*
  137. * Warning: do not read the BCSR registers here
  138. *
  139. * There is a timing bug in the 8349E and 8349EA BCSR code
  140. * version 1.2 (read from BCSR 11) that will cause the CFI
  141. * flash initialization code to overwrite BCSR 0, disabling
  142. * the serial ports and gigabit ethernet
  143. */
  144. puts("Board: Freescale MPC8349EMDS\n");
  145. return 0;
  146. }
  147. /*
  148. * if MPC8349EMDS is soldered with SDRAM
  149. */
  150. #if defined(CONFIG_SYS_BR2_PRELIM) \
  151. && defined(CONFIG_SYS_OR2_PRELIM) \
  152. && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
  153. && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
  154. /*
  155. * Initialize SDRAM memory on the Local Bus.
  156. */
  157. void sdram_init(void)
  158. {
  159. volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  160. volatile fsl_lbc_t *lbc = &immap->im_lbc;
  161. uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
  162. const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 |
  163. LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 |
  164. LSDMR_WRC3 | LSDMR_CL3;
  165. /*
  166. * Setup SDRAM Base and Option Registers, already done in cpu_init.c
  167. */
  168. /* setup mtrpt, lsrt and lbcr for LB bus */
  169. lbc->lbcr = 0x00000000;
  170. /* LB refresh timer prescal, 266MHz/32 */
  171. lbc->mrtpr = 0x20000000;
  172. /* LB sdram refresh timer, about 6us */
  173. lbc->lsrt = 0x32000000;
  174. asm("sync");
  175. /*
  176. * Configure the SDRAM controller Machine Mode Register.
  177. */
  178. /* 0x40636733; normal operation */
  179. lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
  180. /* 0x68636733; precharge all the banks */
  181. lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
  182. asm("sync");
  183. *sdram_addr = 0xff;
  184. udelay(100);
  185. /* 0x48636733; auto refresh */
  186. lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
  187. asm("sync");
  188. /*1 times*/
  189. *sdram_addr = 0xff;
  190. udelay(100);
  191. /*2 times*/
  192. *sdram_addr = 0xff;
  193. udelay(100);
  194. /*3 times*/
  195. *sdram_addr = 0xff;
  196. udelay(100);
  197. /*4 times*/
  198. *sdram_addr = 0xff;
  199. udelay(100);
  200. /*5 times*/
  201. *sdram_addr = 0xff;
  202. udelay(100);
  203. /*6 times*/
  204. *sdram_addr = 0xff;
  205. udelay(100);
  206. /*7 times*/
  207. *sdram_addr = 0xff;
  208. udelay(100);
  209. /*8 times*/
  210. *sdram_addr = 0xff;
  211. udelay(100);
  212. /* 0x58636733; mode register write operation */
  213. lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
  214. asm("sync");
  215. *sdram_addr = 0xff;
  216. udelay(100);
  217. /* 0x40636733; normal operation */
  218. lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
  219. asm("sync");
  220. *sdram_addr = 0xff;
  221. udelay(100);
  222. }
  223. #else
  224. void sdram_init(void)
  225. {
  226. }
  227. #endif
  228. /*
  229. * The following are used to control the SPI chip selects for the SPI command.
  230. */
  231. #ifdef CONFIG_MPC8XXX_SPI
  232. #define SPI_CS_MASK 0x80000000
  233. int spi_cs_is_valid(unsigned int bus, unsigned int cs)
  234. {
  235. return bus == 0 && cs == 0;
  236. }
  237. void spi_cs_activate(struct spi_slave *slave)
  238. {
  239. volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
  240. iopd->dat &= ~SPI_CS_MASK;
  241. }
  242. void spi_cs_deactivate(struct spi_slave *slave)
  243. {
  244. volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
  245. iopd->dat |= SPI_CS_MASK;
  246. }
  247. #endif
  248. #if defined(CONFIG_OF_BOARD_SETUP)
  249. int ft_board_setup(void *blob, struct bd_info *bd)
  250. {
  251. ft_cpu_setup(blob, bd);
  252. #ifdef CONFIG_PCI
  253. ft_pci_setup(blob, bd);
  254. #endif
  255. return 0;
  256. }
  257. #endif