ddr.c 2.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2011 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <fsl_ddr_sdram.h>
  7. #include <fsl_ddr_dimm_params.h>
  8. struct board_specific_parameters {
  9. u32 n_ranks;
  10. u32 datarate_mhz_high;
  11. u32 clk_adjust;
  12. u32 cpo;
  13. u32 write_data_delay;
  14. u32 force_2t;
  15. };
  16. /*
  17. * This table contains all valid speeds we want to override with board
  18. * specific parameters. datarate_mhz_high values need to be in ascending order
  19. * for each n_ranks group.
  20. */
  21. static const struct board_specific_parameters udimm0[] = {
  22. /*
  23. * memory controller 0
  24. * num| hi| clk| cpo|wrdata|2T
  25. * ranks| mhz|adjst| | delay|
  26. */
  27. {2, 300, 4, 4, 2, 0},
  28. {2, 365, 4, 6, 2, 0},
  29. {2, 450, 4, 7, 2, 0},
  30. {2, 850, 4, 31, 2, 0},
  31. {1, 300, 4, 4, 2, 0},
  32. {1, 365, 4, 6, 2, 0},
  33. {1, 450, 4, 7, 2, 0},
  34. {1, 850, 4, 31, 2, 0},
  35. {}
  36. };
  37. void fsl_ddr_board_options(memctl_options_t *popts,
  38. dimm_params_t *pdimm,
  39. unsigned int ctrl_num)
  40. {
  41. const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  42. unsigned int i;
  43. ulong ddr_freq;
  44. if (ctrl_num != 0) /* we have only one controller */
  45. return;
  46. for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
  47. if (pdimm[i].n_ranks)
  48. break;
  49. }
  50. if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) /* no DIMM */
  51. return;
  52. pbsp = udimm0;
  53. /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
  54. * freqency and n_banks specified in board_specific_parameters table.
  55. */
  56. ddr_freq = get_ddr_freq(0) / 1000000;
  57. while (pbsp->datarate_mhz_high) {
  58. if (pbsp->n_ranks == pdimm[i].n_ranks) {
  59. if (ddr_freq <= pbsp->datarate_mhz_high) {
  60. popts->clk_adjust = pbsp->clk_adjust;
  61. popts->cpo_override = pbsp->cpo;
  62. popts->write_data_delay =
  63. pbsp->write_data_delay;
  64. popts->twot_en = pbsp->force_2t;
  65. goto found;
  66. }
  67. pbsp_highest = pbsp;
  68. }
  69. pbsp++;
  70. }
  71. if (pbsp_highest) {
  72. printf("Error: board specific timing not found "
  73. "for data rate %lu MT/s!\n"
  74. "Trying to use the highest speed (%u) parameters\n",
  75. ddr_freq, pbsp_highest->datarate_mhz_high);
  76. popts->clk_adjust = pbsp_highest->clk_adjust;
  77. popts->cpo_override = pbsp_highest->cpo;
  78. popts->write_data_delay = pbsp_highest->write_data_delay;
  79. popts->twot_en = pbsp_highest->force_2t;
  80. } else {
  81. panic("DIMM is not supported by this board");
  82. }
  83. found:
  84. /*
  85. * Factors to consider for half-strength driver enable:
  86. * - number of DIMMs installed
  87. */
  88. popts->half_strength_driver_enable = 0;
  89. popts->dqs_config = 0; /* only true DQS signal is used on board */
  90. }